关于interface中时钟块里的input和output方向

interface dut_in_interface（input bit clk, input bit rst_n）
    logic       in_en  ;
    logic [7:0] in_data;

    clocking drv_cb @(posedge clk)
        default input #1 output #1;

        output in_en  ;
        output in_Data;
    endclocking

    clocking mon_cb @(posedge clk)
        default input #1 output #1;

        input in_en  ;
        input in_Data;
    endclocking

endinterface

interface dut_out_interface（input bit clk, input bit rst_n）
    logic       out_en  ;
    logic [7:0] out_data;

    clocking mon_cb @(posedge clk)
        default input #1 output #1;

        input out_en  ;
        input out_Data;
    endclocking
endinterface