时间基准电路与带使能的多周期计数器仿真
module cnt_sync(CLK,CNTVAL,OV );
input CLK;
output [31:0] CNTVAL;
output OV;
parameter MAX_VAL = 25_000_000;
reg [31:0] CNTVAL;
reg OV;
always @ (posedge CLK) begin
if(CNTVAL >= MAX_VAL)
CNTVAL <= 0;
else
CNTVAL <= CNTVAL + 1'b1;
end
always @ (CNTVAL) begin
if(CNTVAL == MAX_VAL)
OV = 1'b1;
else
OV = 1'b0;
end
endmodule
module cnt_en_0to9(CLK, CNTVAL, EN , OV );
input CLK;
input EN;
output [4-1:0] CNTVAL;
output OV;
reg [4-1:0] CNTVAL;
reg OV;
always @ (posedge CLK) begin
if(EN) begin
if(CNTVAL >= 9)
CNTVAL <= 0;
else
CNTVAL <= CNTVAL + 1'b1;
end
else
CNTVAL <= CNTVAL ;
end
always @ (CNTVAL) begin
if(CNTVAL == 9)
OV = 1'b1;
else
OV = 1'b0;
end
endmodule
module dec_2to4(IN ,OUT);
input [1:0] IN ;
output [3:0] OUT ;
reg [3:0] OUT ;
always @ (IN) begin
case(IN)
2'b00: OUT = 4'b 0001;
2'b01: OUT = 4'b 0010;
2'b10: OUT = 4'b 0100;
2'b11: OUT = 4'b 1000;
endcase
end
endmodule
RTL视图
仿真波形
使用SignalTap观测电路
缺点: (1)同一时刻,只能观测到一个计数值 (2) 不利于调试
解决方法:高级触发方式-分段触发
将计数器的计数范围改为0-15,并在DE0开发板上显示出来
module cnt_sync_1(CLK,CNTVAL,OV );
input CLK;
output [31:0] CNTVAL;
output OV;
parameter MAX_VAL = 25_000_000;
reg [31:0] CNTVAL;
reg OV;
always @ (posedge CLK) begin
if(CNTVAL >= MAX_VAL)
CNTVAL <= 0;
else
CNTVAL <= CNTVAL + 1'b1;
end
always @ (CNTVAL) begin
if(CNTVAL == MAX_VAL)
OV = 1'b1;
else
OV = 1'b0;
end
endmodule
module cnt_en_0to15(CLK, CNTVAL, EN , OV );
input CLK;
input EN;
output [4-1:0] CNTVAL;
output OV;
reg [4-1:0] CNTVAL;
reg OV;
always @ (posedge CLK) begin
if(EN) begin
if(CNTVAL >= 15)
CNTVAL <= 0;
else
CNTVAL <= CNTVAL + 1'b1;
end
else
CNTVAL <= CNTVAL ;
end
always @ (CNTVAL) begin
if(CNTVAL == 15)
OV = 1'b1;
else
OV = 1'b0;
end
endmodule
module yima(in,out);
input[3:0] in;
output[7:0] out;
reg[7:0] out;
always@(in)
begin
case(in)
4'b0000:out=8'b11000000;
4'b0001:out=8'b11111001;
4'b0010:out=8'b10100100;
4'b0011:out=8'b10110000;
4'b0100:out=8'b10011001;
4'b0101:out=8'b10010010;
4'b0110:out=8'b10000010;
4'b0111:out=8'b11111000;
4'b1000:out=8'b10000000;
4'b1001:out=8'b10010000;
4'b1010:out=8'b10001000;
4'b1011:out=8'b10000011;
4'b1100:out=8'b11000110;
4'b1101:out=8'b10100001;
4'b1110:out=8'b10000110;
4'b1111:out=8'b11001110;
endcase
end
endmodule