名称:足球竞赛计时钟设计VHDL代码Quartus仿真(文末获取)
软件:Quartus
语言:VHDL
代码功能:
足球竞赛计时钟设计
任务及要求
CPLD为复杂可编程逻辑器件,通过EDA技术对其进行编程,可将一个较复杂的
数字系统集成于一个芯片中,制成专用集成电路芯片,并可随时在系统修改其逻辑功能。并最终完成电路的编程调试。具体要求如下:
1.用两位BCD码显示足球比分牌
2.通过加分输入可以给A队或B队加分
3.设计对调功能,A队和B队分数互换,意味着中场交换场地
4.显示比赛倒计时功能。
1. 工程文件
2. 程序文件
3. 程序编译
4. RTL图
5. Testbench
6. 仿真图
部分代码展示:
LIBRARY ieee; USE ieee.std_logic_1164.all; --分数对调模块 ENTITY change_score IS PORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; change : IN STD_LOGIC;--对调信号,高电平对调 score_A_H : IN STD_LOGIC_VECTOR(3 DOWNTO 0); score_A_L : IN STD_LOGIC_VECTOR(3 DOWNTO 0); score_B_H : IN STD_LOGIC_VECTOR(3 DOWNTO 0); score_B_L : IN STD_LOGIC_VECTOR(3 DOWNTO 0); score_A_H_dis : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); score_A_L_dis : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); score_B_H_dis : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); score_B_L_dis : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END change_score; ARCHITECTURE behaveral OF change_score IS BEGIN PROCESS (clk, rst) BEGIN IF (rst = '1') THEN--复位 score_A_H_dis <= "0000"; score_A_L_dis <= "0000"; score_B_H_dis <= "0000"; score_B_L_dis <= "0000"; ELSIF (clk'EVENT AND clk = '1') THEN IF (change = '1') THEN--高电平对调,将B分数赋值给A,A给B score_A_H_dis <= score_B_H; score_A_L_dis <= score_B_L; score_B_H_dis <= score_A_H; score_B_L_dis <= score_A_L; ELSE--低电平不对调 score_A_H_dis <= score_A_H; score_A_L_dis <= score_A_L; score_B_H_dis <= score_B_H; score_B_L_dis <= score_B_L; END IF; END IF; END PROCESS; END behaveral;
源代码
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