5.3 verilog参数化设计

关键词：paraamemter， defparam ,

1.模块1对模块2的参数重定义

模块1

module led_run2(
    Clk,
    Reset_n,
    led
);
    input Clk;
    input Reset_n;
    output  [7:0] led;
    
    reg [24:0] counter;
    reg [2:0] counter1; //二进制8个状态,3位
    parameter MCNT = 25'd24999999;
    always@(posedge Clk or negedge Reset_n)
    if(!Reset_n)
        counter <= 0;
    else if(counter == MCNT)
        counter <= 0;
    else
        counter <= counter + 1'd1;
        
    always@(posedge Clk or negedge Reset_n)
    if(!Reset_n)
        counter1 <= 0;
    else if(counter == MCNT)
        counter1 <= counter1 + 1'b1;

    decoder_3_8
    #(
        .WITH(7)
    )
     decode_3_8_inst(
        .a(counter1[2]),    //counter1[2] 是最高位
        .b(counter1[1]),
        .c(counter1[0]),
        .out(led)       //底层已将out定义为reg型，所以顶层不能再定义成reg型
    );
    defparam decode_3_8_inst.WITH = 7; //对底层代码的重定参
endmodule

模块2

module decoder_3_8(
    a,
    b,
    c,
    out
);
    parameter WITH = 4;

    input a;
    input b;
    input c;
    output reg [WITH:0] out;


// 2种写法：reg [7:0] out;

//以always块描述的信号赋值，被赋值对象必须定义为reg类型
//{a,b,c}拼接成了一个三位信号

always@(*)begin
    case({a,b,c})
        3'b000: out = 8'b0000_0001;
        3'b001: out = 8'b0000_0010;
        3'b010: out = 8'b0000_0100;
        3'b011: out = 8'b0000_1000;
        3'b100: out = 8'b0001_0000;
        3'b101: out = 8'b0010_0000;
        3'b110: out = 8'b0100_0000;
        3'b111: out = 8'b1000_0000;
    endcase
end

endmodule

2种定参方法

//第一种重定参方法
    decoder_3_8
    #(
        .WITH(7)
    )


//第二种重定参方法
    defparam decode_3_8_inst.WITH = 7;

2.testbench文件中对模块1中计数器的参数重定义

`timescale 1ns/1ns

module led_run_tb();
    
    reg Clk;
    reg Reset_n;
    wire [7:0]led;

    
    led_run2    //第一种重定参方法
    #(
        .MCNT(2499)
    )
    led_run_inst(
        .Clk(Clk),
        .Reset_n(Reset_n),
        .led(led)
    );
    
//    defparam led_run_inst.MCNT = 2499;    //第二种重定参方法
    
    initial Clk = 1;
    always #10 Clk = ~Clk;
    
    initial begin
        Reset_n = 0;
        #201;
        Reset_n = 1;
        #40000000;
        $stop;
    end
    
endmodule