HDLBits学习笔记（51~60)

HDLBits学习笔记（51~60)

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题目51 Truthtable1

题干：Create a combinational circuit that implements the above truth table.


题目大意：完成如图所示电路。

题目分析：通过真值表获得相应的组合逻辑电路。步骤如下：
1、找到输出值为1的项
2、将每一项输入值为1的信号和输入值为0的信号的非相与
3、再将各项相或

答案：

module top_module( 
    input x3,
    input x2,
    input x1,  // three inputs
    output f   // one output
);
    assign f = ((~x3)&~(x1)&x2)|(x2&x1&(~x3))|(x3&x1&(~x2))|(x1&x2&x3);
endmodule

题目52 Mt2015 eq2

题干：Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and produces an output z. The value of z should be 1 if A = B, otherwise z should be 0.

题目大意：构建一个有两个两位宽的输入信号A,B，和输出信号Z的电路。当A=B时，Z为1，反之Z为0。

题目分析：使用三目运算符可得。

答案：

module top_module ( input [1:0] A, input [1:0] B, output z ); 
    assign z = (A==B)?(1):(0);
endmodule

题目53 Mt2015 q4a

题干：Module A is supposed to implement the function z = (x^y) & x. Implement this module.

题目大意：实现模块A的功能，z = (x^y) & x。

题目分析：直接assign z = (x^y) & x 。

答案：

module top_module (input x, input y, output z);
    assign z = (x^y) & x;
endmodule

题目54 Mt2015 q4b

题干：Circuit B can be described by the following simulation waveform:

题目大意：根据图中所给的仿真波形图构建电路。

题目分析：可以通过波形图发现：输出值为z=1的两种情况：
1.x = 0,y = 0
2.x = 1,y = 1
由此可以获得组合逻辑电路表达式，即同或电路。

答案：

module top_module ( input x, input y, output z );
    assign z = ~x^y;
endmodule

题目55 Mt2015 q4

题干：See mt2015_q4a and mt2015_q4b for the submodules used here. The top-level design consists of two instantiations each of subcircuits A and B, as shown below.Implement this circuit.

题目大意：使用上题设计的AB电路完成图示电路。

题目分析：模块实例化与组合逻辑电路的设计。

答案：

module top_module (input x, input y, output z);
    wire z1,z2,z3,z4;
    a a_instance1(
        .x(x),
        .y(y),
        .z(z1)
    );
    a a_instance2(
        .x(x),
        .y(y),
        .z(z3)
    );
    b b_instance1(
        .x(x),
        .y(y),
        .z(z2)
    );
    b b_instance2(
        .x(x),
        .y(y),
        .z(z4)
    );
    assign z = (z1|z2)^(z3&z4);
endmodule
module a (
	input wire x,
    input wire y,
    output wire z
);
    assign z = (x^y) & x;
endmodule

module b (
	input wire x,
    input wire y,
    output wire z
);
    assign z = ~x^y;
endmodule

题目56 Ringer

题干： Whenever the phone needs to ring from an incoming call (input ring), your circuit must either turn on the ringer (output ringer = 1) or the motor (output motor = 1), but not both. If the phone is in vibrate mode (input vibrate_mode = 1), turn on the motor. Otherwise, turn on the ringer.

题目大意：当手机接到电话时，通过判断是否开启震动模式来设置输出值ringer和motor的状态。

题目分析：状态判断，即当手机来电时，当打开了震动模式，只有电机动，若没打开，只有铃声响。使用三目运算符嵌套。

答案：

module top_module (
    input ring,
    input vibrate_mode,
    output ringer,       // Make sound
    output motor         // Vibrate
);
    assign ringer = ring?((vibrate_mode)?(0):(1)):(0);
    assign motor  = ring?((vibrate_mode)?(1):(0)):(0);
endmodule

题目57 Thermostat

题干：The thermostat can be in one of two modes: heating (mode = 1) and cooling (mode = 0). In heating mode, turn the heater on when it is too cold (too_cold = 1) but do not use the air conditioner. In cooling mode, turn the air conditioner on when it is too hot (too_hot = 1), but do not turn on the heater. When the heater or air conditioner are on, also turn on the fan to circulate the air. In addition, the user can also request the fan to turn on (fan_on = 1), even if the heater and air conditioner are off.

题目大意：恒温器可以工作在两种模式下，分别是加热状态mode = 1,和制冷状态mode = 0。在加热状态时当too_cold=1 时开始加热，使用加热器，不使用空调。在制冷状态时，在too_hot=1时打开空调，不使用加热器。当加热器或者空调正在工作时，也要打开风扇。风扇的启动也可以通过手动控制，fan_on=1。

题目分析：对于这个三个输出。可得真值表。

答案：

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 
    assign heater = (mode)?((too_cold)?(1):(0)):(0);
    assign aircon = (~mode)?((too_hot)?(1):(0)):(0);
    assign fan = heater|aircon|fan_on;
endmodule

题目58 Popcount3

题干：A “population count” circuit counts the number of '1’s in an input vector. Build a population count circuit for a 3-bit input vector.

题目大意：构建一个电路记录3位宽的输入的1的个数。

题目分析：可以用generate-always-for语句实现。

答案：

module top_module( 
    input [2:0] in,
    output [1:0] out );
	integer i;  //前文提过 genvar型变量在always中无法赋值
    generate
        always@(*)begin
            out = 1'b0;
            for(i=0;i<3;i++)begin:pop
                if(in[i])
                    out = out + 1'b1;
                else
                    out = out + 1'b0;
            end
        end
    endgenerate
endmodule

题目59 Gatesv

题干：You are given a four-bit input vector in[3:0]. We want to know some relationships between each bit and its neighbour:

out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left (higher index) are ‘1’. For example, out_both[2] should indicate if in[2] and in[3] are both 1. Since in[3] has no neighbour to the left, the answer is obvious so we don’t need to know out_both[3].
out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are ‘1’. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don’t need to know out_any[0].
out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[2] should indicate if in[2] is different from in[3]. For this part, treat the vector as wrapping around, so in[3]'s neighbour to the left is in[0].

题目大意：对于一个四位宽的输入有三个输出值：
out_both：判断某一位和其相邻的左边(较高位)是否都为一，不关心out_both[3]。
out_any : 判断某一位和其相邻的右边(较低位)是否有一位为一不关心out_any[0]。
out_any : 判断某一位和其相邻的左边(较高位)是否不同。

题目分析：使用 generate-for-assign实现

答案：

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );
    assign out_different[3] = in[3]^in[0];
	genvar i;
    generate
        for(i=0;i<3;i++)begin:aa
            assign out_both[i] = (in[i]==1'b1) & (in[i+1]==1'b1);
            assign out_different[i] = in[i]^in[i+1];
        end
        for(i=1;i<4;i++)begin:bb
            assign out_any[i] = (in[i]==1'b1) | (in[i-1]==1'b1);
        end		
    endgenerate
endmodule

题目60 Gatesv100

题目分析：本题与上题一样，只不过将输入从4位宽改到了100位宽。修改上体i的范围即可。

答案：

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different );
    assign out_different[99] = in[99]^in[0];
	genvar i;
    generate
        for(i=0;i<99;i++)begin:aa
            assign out_both[i] = (in[i]==1'b1) & (in[i+1]==1'b1);
            assign out_different[i] = in[i]^in[i+1];
        end
        for(i=1;i<100;i++)begin:bb
            assign out_any[i] = (in[i]==1'b1) | (in[i-1]==1'b1);
        end		
    endgenerate
endmodule