FPGA project ： example_ip

PLL:

module top(
    input           wire    sys_clk      ,

    output          wire    clk_mul_2    ,
    output          wire    clk_div_2    ,
    output          wire    clk_phase_90 ,
    output          wire    clk_ducyle_2 ,
    output          wire    locked    
);



pll pll_insert(
	.inclk0                  ( sys_clk      ),
	.c0                      ( clk_mul_2    ),
	.c1                      ( clk_div_2    ),
	.c2                      ( clk_phase_90 ),
	.c3                      ( clk_ducyle_2 ),
	.locked                  ( locked       )
    );

endmodule

`timescale 1ns/1ns
module test_pll ();
    reg                 sys_clk         ;
    wire                clk_mul_2       ;
    wire                clk_div_2       ;
    wire                clk_phase_90    ;
    wire                clk_ducyle_2    ;
    wire                locked          ;

top top_insert(
    .sys_clk            ( sys_clk       ) ,

    .clk_mul_2          ( clk_mul_2     ) ,
    .clk_div_2          ( clk_div_2     ) ,
    .clk_phase_90       ( clk_phase_90  ) ,
    .clk_ducyle_2       ( clk_ducyle_2  ) ,
    .locked             ( locked        )    
);

    parameter CYCLE = 20 ;

    initial begin
        sys_clk <= 1'b1 ;
    end
    always #(CYCLE / 2) sys_clk <= ~ sys_clk ;
    
endmodule