vivado 初始化RAM内容

初始化RAM内容

RAM可以通过以下方式初始化：

•在HDL源代码中指定RAM初始内容

•指定外部数据文件中的RAM初始内容

指定HDL源中的RAM初始内容密码

使用信号默认值机制直接在HDL中描述初始RAM内容源代码。

VHDL编码示例

type ram_type is array (0 to 31) of std_logic_vector(19 downto 0);

signal RAM : ram_type :=

(

X"0200A", X"00300", X"08101", X"04000", X"08601", X"0233A", X"00300",

X"08602", X"02310", X"0203B", X"08300", X"04002", X"08201", X"00500",

X"04001", X"02500", X"00340", X"00241", X"04002", X"08300", X"08201",

X"00500", X"08101", X"00602", X"04003", X"0241E", X"00301", X"00102",

X"02122", X"02021", X"0030D", X"08201"

);

All bit positions are initialized to the same value:

type ram_type is array (0 to 127) of std_logic_vector (15 downto 0);

signal RAM : ram_type := (others => (others => '0'));

Verilog Coding Example

All addressable words are initialized to the same value.

reg [DATA_WIDTH-1:0] ram [DEPTH-1:0];

integer i;

initial for (i=0; i<DEPTH; i=i+1) ram[i] = 0;

end

指定外部数据中的RAM初始内容文件

使用HDL源代码中的文件读取功能从外部数据文件。

•外部数据文件是任意名称的ASCII文本文件。

•外部数据文件中的每一行都描述了内存

•外部数据文件中的行数必须与RAM阵列中的行数来表示。一标记的行数不足。

•与给定线路相关的可寻址位置由主线路的方向定义模拟RAM的信号范围。

•您可以用二进制或十六进制表示RAM内容。两者不能兼而有之。

•外部数据文件不能包含任何其他内容，如注释。

以下外部数据文件使用二进制值初始化8 x 32位RAM：

00001110110000011001111011000110

00101011001011010101001000100011

01110100010100011000011100001111

01000001010000100101001110010100

00001001101001111111101000101011

00101101001011111110101010100111

11101111000100111000111101101101

10001111010010011001000011101111

00000001100011100011110010011111

11011111001110101011111001001010

11100111010100111110110011001010

11000100001001101100111100101001

10001011100101011111111111100001

11110101110110010000010110111010

01001011000000111001010110101110

11100001111111001010111010011110

01101111011010010100001101110001

01010100011011111000011000100100

11110000111101101111001100001011

10101101001111010100100100011100

01011100001010111111101110101110

01011101000100100111010010110101

11110111000100000101011101101101

11100111110001111010101100001101

01110100000011101111111000011111

00010011110101111000111001011101

01101110001111100011010101101111

10111100000000010011101011011011

11000001001101001101111100010000

00011111110010110110011111010101

01100100100000011100100101110000

10001000000100111011001010001111

11001000100011101001010001100001

10000000100111010011100111100011

11011111010010100010101010000111

10000000110111101000111110111011

10110011010111101111000110011001

00010111100001001010110111011100

10011100101110101111011010110011

01010011101101010001110110011010

01111011011100010101000101000001

10001000000110010110111001101010

11101000001101010000111001010110

11100011111100000111110101110101

01001010000000001111111101101111

00100011000011001000000010001111

10011000111010110001001011100100

11111111111011110101000101000111

11000011000101000011100110100000

01101101001011111010100011101001

10000111101100101001110011010111

11010110100100101110110010100100

01001111111001101101011111001011

11011001001101110110000100110111

10110110110111100101110011100110

10011100111001000010111111010110

00000000001011011111001010110010

10100110011010000010001000011011

11001010111111001001110001110101

00100001100010000111000101001000

00111100101111110001101101111010

11000010001010000000010100100001

11000001000110001101000101001110

10010011010100010001100100100111

Verilog Code Example

reg [31:0] ram [0:63];

initial begin

$readmemb("rams_20c.data", ram, 0, 63);

end

VHDL Code Example

Load the data as follows:

type RamType is array(0 to 7) of bit_vector(31 downto 0);

impure function InitRamFromFile (RamFileName : in string) return RamType is

FILE RamFile : text is in RamFileName;

variable RamFileLine : line;

variable RAM : RamType;

begin

for I in RamType'range loop

readline (RamFile, RamFileLine);

read (RamFileLine, RAM(I));

end loop;

return RAM;

end function;

signal RAM : RamType := InitRamFromFile("rams_20c.data");

Initializing Block RAM (Verilog)

Filename: rams_sp_rom.v

// Initializing Block RAM (Single-Port Block RAM)

// File: rams_sp_rom

module rams_sp_rom (clk, we, addr, di, dout);

input clk;

input we;

input [5:0] addr;

input [19:0] di;

output [19:0] dout;

reg [19:0] ram [63:0];

reg [19:0] dout;

initial

begin

ram[63] = 20'h0200A; ram[62] = 20'h00300; ram[61] = 20'h08101;

ram[60] = 20'h04000; ram[59] = 20'h08601; ram[58] = 20'h0233A;

ram[57] = 20'h00300; ram[56] = 20'h08602; ram[55] = 20'h02310;

ram[54] = 20'h0203B; ram[53] = 20'h08300; ram[52] = 20'h04002;

ram[51] = 20'h08201; ram[50] = 20'h00500; ram[49] = 20'h04001;

ram[48] = 20'h02500; ram[47] = 20'h00340; ram[46] = 20'h00241;

ram[45] = 20'h04002; ram[44] = 20'h08300; ram[43] = 20'h08201;

ram[42] = 20'h00500; ram[41] = 20'h08101; ram[40] = 20'h00602;

ram[39] = 20'h04003; ram[38] = 20'h0241E; ram[37] = 20'h00301;

ram[36] = 20'h00102; ram[35] = 20'h02122; ram[34] = 20'h02021;

ram[33] = 20'h00301; ram[32] = 20'h00102; ram[31] = 20'h02222;

ram[30] = 20'h04001; ram[29] = 20'h00342; ram[28] = 20'h0232B;

ram[27] = 20'h00900; ram[26] = 20'h00302; ram[25] = 20'h00102;

ram[24] = 20'h04002; ram[23] = 20'h00900; ram[22] = 20'h08201;

ram[21] = 20'h02023; ram[20] = 20'h00303; ram[19] = 20'h02433;

ram[18] = 20'h00301; ram[17] = 20'h04004; ram[16] = 20'h00301;

ram[15] = 20'h00102; ram[14] = 20'h02137; ram[13] = 20'h02036;

ram[12] = 20'h00301; ram[11] = 20'h00102; ram[10] = 20'h02237;

ram[9] = 20'h04004; ram[8] = 20'h00304; ram[7] = 20'h04040;

ram[6] = 20'h02500; ram[5] = 20'h02500; ram[4] = 20'h02500;

ram[3] = 20'h0030D; ram[2] = 20'h02341; ram[1] = 20'h08201;

ram[0] = 20'h0400D;

end

always @(posedge clk)

begin

if (we)

ram[addr] <= di;

dout <= ram[addr];

end

endmodule

Initializing Block RAM (VHDL)

Filename: rams_sp_rom.vhd

-- Initializing Block RAM (Single-Port Block RAM)

-- File: rams_sp_rom.vhd

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity rams_sp_rom is

port(

clk : in std_logic;

we : in std_logic;

addr : in std_logic_vector(5 downto 0);

di : in std_logic_vector(19 downto 0);

do : out std_logic_vector(19 downto 0)

);

end rams_sp_rom;

architecture syn of rams_sp_rom is

type ram_type is array (63 downto 0) of std_logic_vector(19 downto 0);

signal RAM : ram_type := (X"0200A", X"00300", X"08101", X"04000", X"08601",

X"0233A",

X"00300", X"08602", X"02310", X"0203B", X"08300", X"04002",

X"08201", X"00500", X"04001", X"02500", X"00340", X"00241",

X"04002", X"08300", X"08201", X"00500", X"08101", X"00602",

X"04003", X"0241E", X"00301", X"00102", X"02122", X"02021",

X"00301", X"00102", X"02222", X"04001", X"00342", X"0232B",

X"00900", X"00302", X"00102", X"04002", X"00900", X"08201",

X"02023", X"00303", X"02433", X"00301", X"04004", X"00301",

X"00102", X"02137", X"02036", X"00301", X"00102", X"02237",

X"04004", X"00304", X"04040", X"02500", X"02500", X"02500",

X"0030D", X"02341", X"08201", X"0400D");

begin

process(clk)

begin

if rising_edge(clk) then

if we = '1' then

RAM(to_integer(unsigned(addr))) <= di;

end if;

do <= RAM(to_integer(unsigned(addr)));

end if;

end process;

end syn;

Initializing Block RAM From an External Data File (Verilog)

Filename: rams_init_file.v

// Initializing Block RAM from external data file

// Binary data

// File: rams_init_file.v

module rams_init_file (clk, we, addr, din, dout);

input clk;

input we;

input [5:0] addr;

input [31:0] din;

output [31:0] dout;

reg [31:0] ram [0:63];

reg [31:0] dout;

initial begin

$readmemb("rams_init_file.data",ram);

end

always @(posedge clk)

begin

if (we)

ram[addr] <= din;

dout <= ram[addr];

end endmodule

Initializing Block RAM From an External Data File (VHDL)

Filename: rams_init_file.vhd

-- Initializing Block RAM from external data file

-- File: rams_init_file.vhd

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use std.textio.all;

entity rams_init_file is

port(

clk : in std_logic;

we : in std_logic;

addr : in std_logic_vector(5 downto 0);

din : in std_logic_vector(31 downto 0);

dout : out std_logic_vector(31 downto 0)

);

end rams_init_file;

architecture syn of rams_init_file is

type RamType is array (0 to 63) of bit_vector(31 downto 0);

impure function InitRamFromFile(RamFileName : in string) return RamType is

FILE RamFile : text is in RamFileName;

variable RamFileLine : line;

variable RAM : RamType;

begin

for I in RamType'range loop

readline(RamFile, RamFileLine);

read(RamFileLine, RAM(I));

end loop;

return RAM;

end function;

signal RAM : RamType := InitRamFromFile("rams_init_file.data");

begin

process(clk)

begin

if clk'event and clk = '1' then

if we = '1' then

RAM(to_integer(unsigned(addr))) <= to_bitvector(din);

end if;

dout <= to_stdlogicvector(RAM(to_integer(unsigned(addr))));

end if;

end process;

end syn;