verilog paramer array的定义和使用

问题描述：

在UVM验证环境中定义类A，parameter定义如下：

parameter A1 = 100；
parameter int B[6] = '{32h'01,32h'02,32h'03,32h'04,32h'05,32h'06};

在top.sv中引用 parameter A1，如下：

generate
	for (genvar ii = 0; i < A::A1; i++) begin: apb_loop_if
		svt_apb_if sys_apb_if();
	end
endgenerate

编译结果：

报segmentation fault。

问题追踪

https://stackoverflow.com/questions/23507629/parameter-array-in-verilog

The given example is assigning unpacked values to packed parameter array. This in not allowed with Verilog.

Verilog only support simple vector based parameters. It does not support unpacked arrays. SystemVerilog, which superseded Verilog, does support parameter arrays. Almost all modern Verilog simulators are really SystemVerilog simulators (at least for the commercial simulators; open source simulators have incomplete support). To have your files read as SystemVerilog, change the file extension for .v to .sv. Then you can assign unpacked to a 2 dimensional parameter array:

parameter [7:0] PARAM_ARRAY [TOTAL-1 : 0]   = {8'd1, 8'd0, 8'd0, 8'd2};

Type names are also allowed. For example, using integer to creates a 32x4 array:

parameter integer PARAM_ARRAY [TOTAL-1 : 0]   = {1, 0, 0, 2};

This is documented in:
IEEE Std 1364-2001 § 3.11 Parameters
IEEE Std 1364-2005 § 4.10 Parameters
(SystemVerilog) IEEE Std 1800-2012 § 6.20 Constants
As a pure Verilog solution, you will need to created one long vector:

parameter [8*TOTAL-1:0] PARAM_ARRAY = {8'd1, 8'd0, 8'd0, 8'd2};

Then access with a slice as hard coded PARAM_ARRAY[7:0] or using the +:: PARAM_ARRAY[8*index +: 8]. Note that +: requires Verilog-2001 or higher (which even most open-source simulators support). Indexing vectors and arrays with +: