FPGA中函数使用

定义输入为x，输出为count；则：

function  [7:0] get0;

    input [7:0] x;
    reg  [7:0] count;

    integer    i;

    begin
        count = 0;
        for(i=0;i<7;i=i+1)
            if(x[i]=1'b0)
                count = count + 1;
        get0 = count;
    end
endfunction

用函数和case语句描述的编码器（不含优先顺序）

module    code_83(din,dout);

    input    [7:0] din;

    output    [2:0] dout;

function    [2:0] code;    //函数定义
    input    [7:0] din;    //函数只有输入，输出为函数名本身

    output    [2:0] dout;

        casex(din)
            8'b1xxx_xxxx: code = 3'h7;
            8'b01xx_xxxx: code = 3'h6;
            8'b001x_xxxx: code = 3'h5;
            8'b0001_xxxx: code = 3'h4;
            8'b0000_1xxx: code = 3'h3;
            8'b0000_01xx: code = 3'h2;
            8'b0000_001x: code = 3'h1;
            8'b0000_000x: code = 3'h0;
            default: code = 3'hx;
        endcase
endfunction

assign  dout = code(din);

endmodule