因为输入是239个,输出是255个,所以实际工程中使用需要用到FIFO,这里只是测试RS编码功能,没用FIFO。
端口:
时序图:
The in_startofpacket signal starts a codeword; the in_endofpacket signals its termination. An asserted in_valid signal indicates valid data. The in_startofpacket signal is only valid when you assert the in_valid signal. For a 1-channel codeword, assert the in_startofpacket and in_endofpacket
signals for one clock cycle.
IP配置
RS(255,239)
握手程序
控制时序图中的高亮信号。
module RS_en(
clk,rst_n,dout
);
input clk,rst_n;
output wire [7:0] dout;
```c
//计数值作为输入数据
reg [7:0] cnt_d;
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
cnt_d <= 0;
else if(cnt_d==300)
cnt_d <= 0;
else
cnt_d <= cnt_d +1;
end
//调用ip核的握手信号
reg [7:0] cnt;
wire add_cnt,end_cnt;
reg in_valid,in_start,in_end;
wire in_ready; // .ready
wire out_startofpacket; // out.startofpacket
wire out_endofpacket; // .endofpacket
wire out_valid; // .valid
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
cnt <= 0;
else if(add_cnt)begin
if(end_cnt)
cnt <= 0;
else
cnt <= cnt + 1'b1;
end
end
assign add_cnt = 1;
assign end_cnt = add_cnt && cnt== 239; //1~239
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0)
in_valid <= 0;
else if(add_cnt && cnt==0)
in_valid <= 1;
end
always @(posedge clk or negedge rst_n)begin
if(rst_n==1'b0) begin
in_start <= 0;
in_end <= 0;
end
else if(add_cnt && cnt==0)
in_start <= 1;
else if(add_cnt && cnt== 238)
in_end <= 1;
else begin
in_start <= 0;
in_end <= 0;
end
end
RS_encode Rs_encode_inst (
.clk_clk (clk), // clk.clk
.reset_reset_n (rst_n), // reset.reset_n
.in_startofpacket (in_start), // in.startofpacket
.in_endofpacket (in_end), // .endofpacket
.in_valid (in_valid), // .valid
.in_ready (in_ready), // .ready
.in_data (cnt_d), // .data
.out_startofpacket (out_startofpacket), // out.startofpacket
.out_endofpacket (out_endofpacket), // .endofpacket
.out_valid (out_valid), // .valid
.out_ready (1'b1), // .ready
.out_data (dout) // .data
);
endmodule
仿真结果
cnt_d计数值作为输入数据 1~239
dout前239位与cnt_d保持一致(延迟两拍输出),后16位是RS编码后生成的纠错码,图2中的37~148。