静态时序分析时可能遇到的问题及原因

1.大的延迟和大的转换时间

当发现slack为负时，要检查线网上有没有很大的延迟和很大转换时间，如果有那么可能是以下原因引起的：

a：高扇出

b：long nets：长连线--需要插入buffer来解决较长的连线

c：low strength cells：cells which may not have been replaced because these are labeled as dont touch in the design.

d：memory path：paths that typically fail due to large setup times on memory inputs and large output delays on memory outputs.

2.多周期路径问题

For a multicycle N setup specification, it is common to see the corresponding multicycle N-1 hold specification missing. Consequently, this can cause
a large number of unnecessary delay cells to get inserted when a tool is fixing the hold violations.

3.路径没有优化

STA违例可能出现在没有优化的路径，可通过检查数据路径来检查这种情形。单元是否有很大延迟？可不可以手动优化这些数据路径？

4.路径仍热不满足时序

如果路径有很强的单元驱动但还是不满足时序，那么就需要检查延迟和线负载大的引脚。把单元放置近一些可能就会使延