搭建一个UVM环境(一) 基本验证环境

interface

    uvm里面interface与systemverilog的是一样的，在这里就不做介绍；

interface adder_if #(parameter DA_WID=10)(input clk)
    logic [DA_WID-1:0] data_a ;
    logic [DA_WID-1:0] data_b ;
endinterface

transaction

    uvm里面的transaction与systemverilog一致，将总线处理抽象化为一个事务；但是uvm加入了filed_automation机制，使用该机制可以使用一些uvm自带函数，可以简化其他组件的处理；

class adder_tran extends uvm_sequence_item;
    rand bit [10:0] data_a ;
    rand bit [10:0] data_b ;
    `uvm_object_utils_begin(adder_tran)           //filed_automation机制
        `uvm_filed_int(data_a,UVM_ALL_ON)
        `uvm_filed_int(data_b,UVM_ALL_ON)
    `uvm_object_utils_end

    extern function new(string name="");
endclass

function adder_tran::new(string name="");
    super.new(name);
endfunction : new

driver

    UVM里面的driver存在一些特殊的处理，其中get_next_item用来获取下一个transaction，item_done表明当前transaction处理完成了；seq_item_port与sequencer连接，保证sequence与driver之间能够transaction产生和消耗能够同步起来。

class adder_driver extends uvm_driver #(adder_tran);
    `uvm_component_utils(adder_driver)
    virtual adder_if vif ;
    extern function new(string name,uvm_component parent);
    extern function bulid_phase(uvm_phase phase);
    extern task run_phase(uvm_phase phase);
    extern task tran_drive();
endclass : adder_driver

function adder_driver::new(string name,uvm_component parent);
    super.new(name,parent);
endfunction : new

function adder_driver::bulid_phase(uvm_phase phase);
    if(!uvm_config_db #(virtual adder_if)::get(this,"","vif",vif))
        `uvm_error(get_full_name(),"adder_if not get")
endfunction : build_phase

task adder_driver::run_phase(uvm_phase phase);
    while(1) begin
        seq_item_port.get_next_item(req);   //获取下一个tran
        tran_drive();
        seq_item_port.item_done();          //通知sequencer当前tran处理完成
    end
endtask : run_phase

task adder_driver::tran_drive();
    int gap;
    @(posedge clk);
    vif.data_a <= req.data_a;
    vif.data_b <= req.data_b;
    vif.valid  <= 1'b1      ;
    gap = $urandom_range(1,10);
    repeat(gap) begin
        @(posedge clk);
        vif.valid  <= 1'b0      ;
    end
endtask : tran_drive

sequencer

    sequencer是driver和sequence之间的桥梁；sequence负责产生transaction；driver负责将transaction发送到interface上面；而sequencer负责将sequence产生的transaction发给driver。同时sequence之间的仲裁也在sequencer内实现。

class adder_sequencer extends uvn_sequencer #(adder_tran)
    `uvm_component_utils(adder_sequencer)
     function new(string name,uvm_component parent);
         super.new(name,parent);
     endfunction
endclass : adder_sequencer

sequence

    sequence是产生transaction的地方；start_item和finish_item它们利用m_sequencer完成driver和sequence之间的交互；m_sequencer是uvm_sequencer_base，指向了start和`u