Verilog Language-----Basics

simple wire

module top_module( input in, output out );
wire rhs;
    assign rhs = in;
    assign out = rhs;
    
endmodule

Four wires

module top_module( 
    input a,b,c,
    output w,x,y,z );
    wire aw;
    wire bw;
    wire cw;
    assign aw = a;
    assign w = aw;
    
    assign bw = b;
    assign x = bw;
    assign y = bw;
    
    assign cw = c;
    assign z = cw;

endmodule

Inverter

module top_module( input in, output out );
wire rhs;
assign rhs = in;
assign out = ~rhs;
endmodule

AND gate

module top_module( 
    input a, 
    input b, 
    output out );

    assign out=a&b;
endmodule

NOR gate

module top_module( 
    input a, 
    input b, 
    output out );
    
    assign out = ~(a|b);

endmodule

XNOR gate

module top_module( 
    input a, 
    input b, 
    output out );

    assign out=~(a^b);
endmodule

Declaring wires

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 
    
    wire st,nd,rd;
    assign out = rd;
    assign out_n = ~rd;
    assign rd = st|nd;
    assign st = a&b;
    assign nd = c&d;

endmodule

7458chip

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
    
    wire st,nd,rd,th;
    assign st = p2a & p2b;
    assign nd = p2c & p2d;
    assign p2y = st | nd;
    
    assign rd = p1a & p1c &p1b;
    assign th = p1f & p1e &p1d;
    assign p1y = rd | th;


endmodule