#VCS# 关于fsdb波形记载的几种方法

今天，我们总结一下在仿真验证过程中，我们一般常用的几种加载 FSDB波形文件的方法。

This topic describes the use model to dump an FSDB file using VHDL procedures, Verilog system tasks, or UCLI.

情形1：Using VHDL Procedures

 实现（1）：

You can use the VHDL procedures fsdbDumpfile() and fsdbDumpvars() in your VHDL code to dump an FSDB file.

Note: 
To use these procedures, you should include SYNOPSYS library in your VHDL file as follows:
    --Your VHDL file
    library SYNOPSYS;
    use SYNOPSYS.novas.all;
    entity test is
    ...
    end test;
    architecture arch of test is
     ...
    end arch;

方法（2）：

You can use the Verdi provided VHDL file: compile the Verdi provided VHDL file $VERDI_HOME/$VERDI_LIB/novas.vhd using the VCS analyzer and vhdlan, and save it in the same directory where the design is saved. The novas.vhd VHDL file contains the definitions of the FSDB foreign functions.Use the novas package in any VHDL design file that invokes FSDB foreign functions. 

举例：
     use work.novas.all;     --using novas package. 
     entity testbench is end; 
     architecture blk testbench is Begin 
     ... 
     Process begin: dump    
      fsdbDumpvars(0,  : , +fsdbfile+signal.fsdb );  -- call 
       VHDL procedure wait;  
     end process end;

情形2：Using Verilog System Tasks

You can use the Verilog system tasks $fsdbDumpfile() and $fsdbDumpvars() in your Verilog design to dump an FSDB file (see “Using VHDL Procedures or Verilog System Tasks” ).

情形3：Using UCLI