vivado中制作自己的IP核

1.制作

如将下面的代码做成自己的IP核，一个138译码器

module v74x138(
    input g1,
    input g2a_l,
    input g2b_l,
    input [2:0] a,
    output reg [7:0] y_l
    );

always @(g1 or g2a_l or g2b_l or a) begin
    if (g1 && ~g2a_l && ~g2b_l)
    case(a)
        7: y_l = 8'b01111111;
        6: y_l = 8'b10111111;
        5: y_l = 8'b11011111;
        4: y_l = 8'b11101111;
        3: y_l = 8'b11110111;
        2: y_l = 8'b11111011;
        1: y_l = 8'b11111101;
        0: y_l = 8'b11111110;
        default: y_l = 8'b11111111;
    endcase
    else
        y_l = 8'b11111111;
end

endmodule

经过仿真，综合，下载发现这个代码可以正常运行，接下来
点击Tools -> Create and Package new IP，打开一个窗口，next -> 选择 Package your current project(包装当前的项目) -> 选择 include .xci file 这是一个IP核标准文件，里面包含这个IP的所有信息 -> 点击next，如果这个IP之前存在，则会出现overwrite的选项。
这是弹出一个窗口：

这个窗口中可以填写IP核相关的信息。如果中间有修改，还要点击Review and Package的Package IP。

2.在代码中引用

在vivado中，IP catalog中加载了默认的IP核，但其中没有我们刚才制作的。
这时找见Settings -> IP -> Repository，点击“+”号可以添加刚才制作的IP核。随后在IP catalog中双击加入的IP核，选择out-of-context，
在Sources中点击IP核，可以看到出现了以下的代码：

// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved.
// 
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
// 
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
// 
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
// 
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// 
// DO NOT MODIFY THIS FILE.


// IP VLNV: xilinx.com:user:v74x138:1.0
// IP Revision: 2

(* X_CORE_INFO = "v74x138,Vivado 2018.3" *)
(* CHECK_LICENSE_TYPE = "v74x138_0,v74x138,{}" *)
(* CORE_GENERATION_INFO = "v74x138_0,v74x138,{x_ipProduct=Vivado 2018.3,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=v74x138,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}" *)
(* IP_DEFINITION_SOURCE = "package_project" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
///这段代码很重要
module v74x138_0 (
  g1,
  g2a_l,
  g2b_l,
  a,
  y_l
);
/
input wire g1;
input wire g2a_l;
input wire g2b_l;
input wire [2 : 0] a;
output wire [7 : 0] y_l;

  v74x138 inst (
    .g1(g1),
    .g2a_l(g2a_l),
    .g2b_l(g2b_l),
    .a(a),
    .y_l(y_l)
  );
endmodule

复制斜线框住的部分，按照引用模块的方式添加入代码中

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Design Name: 
// Module Name: p_dsbjq_useip
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module p_dsbjq_useip(
    input a,
    input b,
    input c,
    output f
    );
    
wire [7:0] y_l;
assign f = ~(y_l[3] & y_l[5] & y_l[6] & y_l[7]);


// call IP cell    
v74x138_0 uut(
  .g1(1),
  .g2a_l(0),
  .g2b_l(0),
  .a({c, b, a}),
  .y_l(y_l)
);
endmodule