牛客网Verilog刷题——VL37

题目

  请使用D触发器设计一个同时输出2/4/8分频的50%占空比的时钟分频器，注意rst为低电平复位。信号示意图：

  波形示意图如下：

  输入输出描述：

信号	类型	输入/输出	位宽	描述
clk	wire	Intput	1	系统时钟信号
rst	wire	Intput	1	异步复位信号，低电平有效
clk_out2	reg	Output	1	2分频时钟信号
clk_out4	reg	Output	1	4分频时钟信号
clk_out8	reg	Output	1	8分频时钟信号

答案

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
reg	[2:0]	cnt;
reg			sr_clk_out2;
reg			sr_clk_out4;
reg			sr_clk_out8;

//分频计数器
always @(posedge clk_in or negedge rst)
	if(!rst)
		cnt <= 'd0;
	else if(cnt == 'd7)
		cnt <= 'd0;
	else
		cnt <= cnt + 1'd1;

//二分频时钟
always @(posedge clk_in or negedge rst)
	if(!rst)
		sr_clk_out2 <= 1'b0;
	else 
		sr_clk_out2 <= ~sr_clk_out2;

//四分频时钟		
always @(posedge clk_in or negedge rst)
	if(!rst)
		sr_clk_out4 <= 1'b0;
	else if(cnt=='d0 || cnt=='d2 || cnt=='d4 || cnt=='d6)
		sr_clk_out4 <= ~sr_clk_out4;
	else
		sr_clk_out4 <= sr_clk_out4;

//八分频时钟
always @(posedge clk_in or negedge rst)
	if(!rst)
		sr_clk_out8 <= 1'b0;
	else if(cnt=='d0 || cnt=='d4)
		sr_clk_out8 <= ~sr_clk_out8;
	else
		sr_clk_out8 <= sr_clk_out8;

assign clk_out2 = sr_clk_out2;
assign clk_out4 = sr_clk_out4;
assign clk_out8 = sr_clk_out8;
//*************code***********//
endmodule