时钟分频（偶数）

时钟分频（偶数）

题目描述
请使用D触发器设计一个同时输出2/4/8分频的50%占空比的时钟分频器
注意rst为低电平复位。

信号示意图：

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//

    reg[2:0] cnt;
    always@(posedge clk_in or negedge rst)
        begin
            if(!rst)
                cnt <= 3'b0;
            else if(cnt == 3'd7)
                cnt <= 3'b0;
            else
                cnt <= cnt + 1'b1;
        end
    
    reg clk_out2_reg;
    reg clk_out4_reg;
    reg clk_out8_reg;
    
    always@(posedge clk_in or negedge rst)
        begin
            if(!rst)
                clk_out2_reg <= 1'b0;
            else if(cnt == 3'd0 || cnt == 3'd2 || cnt == 3'd4 || cnt == 3'd6)
                clk_out2_reg <= 1'b1;
            else 
                clk_out2_reg <= 1'b0;                
        end
    
    always@(posedge clk_in or negedge rst)
        begin
            if(!rst)
                clk_out4_reg <= 1'b0;
            else if(cnt == 3'd0 || cnt == 3'd1 || cnt == 3'd4 || cnt == 3'd5)
                clk_out4_reg <= 1'b1;
            else 
                clk_out4_reg <= 1'b0;                
        end
    
    always@(posedge clk_in or negedge rst)
        begin
            if(!rst)
                clk_out8_reg <= 1'b0;
            else if(cnt == 3'd0 || cnt == 3'd1 || cnt == 3'd2 || cnt == 3'd3)
                clk_out8_reg <= 1'b1;
            else 
                clk_out8_reg <= 1'b0;                
        end
    
    assign clk_out2 = clk_out2_reg;
    assign clk_out4 = clk_out4_reg;
    assign clk_out8 = clk_out8_reg;

//*************code***********//
endmodule

方法二

`timescale 1ns/1ns
module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );


    reg [2:0]cnt;
    always@(posedge clk_in or negedge rst)
        if(!rst)
            cnt <= 3'b011;
    else
        cnt <= cnt+1;
    
    assign clk_out2 = ~cnt[0];
    assign clk_out4 = ~cnt[1];
    assign clk_out8 = cnt[2];
endmodule