Verilog 刷题-Exams/2013 q2afsm

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input [3:1] r,   // request
    output [3:1] g   // grant
); 
    reg [1:0]next_state,state;
    parameter a=0,b=1,c=2,d=3;
    always@(*)begin 
        case(state)
            a:if(r[1]) next_state <=b;
                else if(r[2])next_state <= c;
                else if (r[3]) next_state <=d;
                else  next_state = a;
            b:next_state = r[1]?b:a;
            c:next_state = r[2]?c:a;
            d:next_state = r[3]?d:a;
        endcase
    end
    always@(posedge clk)begin 
        if(~resetn)state <= a;
        else state<= next_state;
      
    end
    always@(*)begin 
         case(state)
            b:g<=3'b001;
            c:g<=3'b010;
            d:g<=3'b100;
            a:g<=3'b000;
        endcase
    end
endmodule