牛客网verilog VL8 使用generate…for语句简化代码

`timescale 1ns/1ns
module gen_for_module( 
    input [7:0] data_in,
    output [7:0] data_out
);
reg [7:0] data_out;//注意写位宽
integer i;
always@(*) begin
    for(i=0;i<=7;i=i+1)
        data_out[i]=data_in[7-i];
end
 
endmodule