module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done); //
parameter [1:0] b1=2'b00, b2=2'b01, b3=2'b10, d=2'b11;
reg [1:0] state, next_state;
always @(*) begin
case(state)
b1: next_state <= b2;
b2:next_state <= b3;
b3: if(in[3]==1'b1)
next_state <= b1;
else next_state <= d;
d: if(in[3]==1'b1)
next_state <= b1;
else next_state <= d;
// State transition logic (combinational)
endcase
end
always @(posedge clk) begin
if(reset)
state <= d;
else
state <= next_state;
end // State flip-flops (sequential)
// Output logic
assign done = (state == b3);
endmodule
Fsm ps2
最新推荐文章于 2024-10-13 23:48:52 发布