编译好Verilog文件后(module名与文件名一致)
点击Processing 》Start 》Start Test Bench Template Writer创建testbench的.vt文件
自动保存在工程目录下的simulation/modelsim文件夹下,打开编辑
`timescale 1 ps/ 1 ps
module kechengsheji_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg A;
reg B;
reg C;
reg D;
reg E;
// wires
wire L;
wire W;
// assign statements (if any)
kechengsheji i1 (
// port map - connection between master ports and signals/registers
.A(A),