Xilinx 7系列FPGA config设计文档

xilinx FPGA由于掉电擦除的特性，需要每次上电加载配置文件，具体的配置路径有三种，通过jtag来进行下载，通过FLASH来下载，以及通过外部的处理器来下载（ such as a microprocessor, DSP processor, microcontroller, PC, or board tester）。具体配置模式如下：

• Master-Serial configuration mode

• Slave-Serial configuration mode

• Master SelectMAP (parallel) configuration mode (x8 and x16)

• Slave SelectMAP (parallel) configuration mode (x8, x16, and x32)

• JTAG/boundary-scan configuration mode

• Master Serial Peripheral Interface (SPI) flash configuration mode (x1, x2, x4)

• Master Byte Peripheral Interface (BPI) flash configuration mode (x8 and x16) using

parallel NOR flash

 

配置模式的选择是通过multifunction Pin来决定的，M2，M1,M0, should be set at a

constant DC voltage level, either through pull-up or pull-down resistors (≤ 1 kΩ), or tied

directly to ground or VCCO_0.

具体配置模式表如下：

考虑到具体配置使用的时候很多管脚并没有用，因此贴下配置的具体的管脚对应表

   

    

 

 

具体的配置的电路图如下

JTAG单一器件配置电路图

多器件的jtag链电路图

 

作为从设备串行配置电路图，

从设备串行链配置电路图

作为从设备并行数据配置电路图，

多器件通过8bit select MAP配置电路图

SPI flash配置电路图

BPI flash异步读取电路图

BPI flash同步读取电路图

并行菊花链配置方式（第一个通过flash配置，第二个开始通过串行菊花链配置）

多器件配置相同bit文件电路图

 

配置管脚具体信息和连接注意事项

Pin Name	Bank(1)	Type	Direction	Description	描述
CFGBVS	0	Dedicated	Input	Configuration Banks Voltage Select CFGBVS determines the I/O voltage operating range and voltage tolerance for the dedicated configuration bank 0 and for the multi-function configuration pins in banks 14 and 15 in the Spartan-7, Artix-7 and Kintex-7 families. CFGBVS selects the operating voltage for the dedicated bank 0 at all times in all 7 series devices. CFGBVS selects the operating voltage for the multi-function configuration banks 14 and 15 only during configuration. Connect CFGBVS High or Low per the bank voltage requirements. If the VCCO_0 supply for bank 0 is supplied with 2.5V or 3.3V, then the CFGBVS pin must be tied High (i.e. connected to VCCO_0). Tie CFGBVS to Low (i.e. connected to GND), only if the VCCO_0 for bank 0 is less than or equal to 1.8V. If used during configuration, banks 14 and 15 should match the VCCO level applied to bank 0. Caution! To avoid device damage, CFGBVS must be connected correctly to either VCCO_0 or GND. See Configuration Banks Voltage Select, page 32 for more information. Note: The CFGBVS pin is not available on Virtex-7 HT devices. Virtex-7 HT devices support only 1.8V/1.5V operation for bank 0.	用来决定bank0和bank14、15的配置管脚的电压范围 如果bank0是2.5V或3.3V供电，则接高电平 如果1.8V供电，接低电平
M[2:0]	0	Dedicated	Input	Configuration Mode M[2:0] determine the configuration mode. See Table 2-3