vivado error 使用笔记

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Description

I have created an IP core, using Manage IP or from a project IP catalog targeting a specific part. Then, when I read the IP core (read_ip) in Non-project mode Tcl script or Manage IP=>Open_Previously_Created_IP, the part for the IP core does not appear to be correct. The IP core targets are generated for the wrong part (e.g., xc7vx485tffg1157-1), instead of the device I selected.

Vivado issues messages similar to the following examples:

Example 1

WARNING: [IP_Flow 19-1100] IP 'blk_mem_gen_v7_3_0' does not match the current project part 'xc7vx485tffg1157-1'. You can continue to use existing outputs but part differences may result in undefined behavior. Please review your project settings if this is unexpected."

An error will result if the IP in use does not support the xc7vx485tffg1157-1 device.

Example 2
"Generating IP 'my_core' ... 
 Delivering 'Synthesis' files for IP 'My_core'.
 Error: [Xilinx.com:ip:mig_7series:2.0-0] my_core: Target FPGA device"xc7k325t' provided by the mig project did not match with the selected FPGA device 'xc7vx485t' in the project settings. Please cross check the MIG project loader or review the project settings"

Solution

Even though the Vivado tool is being run in "Non-project" mode, there is a pseudo project being created and used by Vivado. The pseudo project will have less automated control over files and flow management.
The problem is a combination of two things:

• The device / part setting for this pseudo project is set to the default part (xc7vx485tffg1157-1 in most cases).
• The generation of the IP core targets uses the project part instead of the part found in the core's XCI file.

If the created IP core device is anything other than the default, there will be a device mismatch with generated warnings or errors.

The simple way to work around this issue is to run a set_property Tcl command before reading the IP cores. For example, the command "set_property part xc7k325tfbg900-2 [current_project]" is run before the read_ip commands.

In Vivado 2013.3, the IP association of IP core device and project device will be changed to require the user to issue a command to generate IP core targets in non-project mode. This will eliminate the issue described above and bring the IP related flows more in alignment with the general non-project mode use model which is intended to give the user more control of (and generally requires a user to control) the management of the files and operations.

Synthesis ignores the 'synth_design -part' argument when checking IP

Options

‎03-06-2014 02:26 PM

Two issues to report:
1. Synthesis ignores the 'synth_design -part' argument and instead uses the project part property when checking IP
2. Vivado non-project mode defaults the project part property to xc7k70tfbg676 unless specifically overwritten.

 

In our design all IP is created for a 7k160t device. 
The tcl build script reads all the IP & design files, then runs synthesis.

...
read_ip "../Vivado_IP/ADC_8kx18_fifo/ADC_8kx18_fifo.xci"
synth_design -part xc7k160tffg676-1 ... 
...

 

I get the following warning in the log file:

WARNING: [IP_Flow 19-2162] IP 'ADC_8kx18_fifo' is locked. Locked reason: Current project part 'xc7k70tfbg676-1' and the part 'xc7k160tffg676-1' used to customize the IP 'ADC_8kx18_fifo' do not match. Please select 'Report IP Status' from the 'Tools/Report' menu.

 

Just to clarify, the IP was created with the same 7k160t device that gets specified in the synth_design -part xc7k160tffg676-1 ...

 

To avoid this, I've had to specify the part property before calling synthesis.

 

set part=xc7k160tffg676-1
set_property part $part [current_project]
...
read_ip "../Vivado_IP/ADC_8kx18_fifo/ADC_8kx18_fifo.xci"
synth_design -part xc7k160tffg676-1 ... 
...