Format :full
DC_MISS_(R|W),CY=cyclenum,TH=tnum,PC=addr,VA=addr, PA=addr,WAY=val
where:(R|W)
Access: R=Read data, W=Write data
CY=cyclenum
Cycle number(decimal)
TH=tnum
Hardware thread number(decimal)
PC=addr
Instruction address when miss occurred(hexadecimal with leading 0x)
VA=addr
Virtual address that missed(hexadecimal with leading 0x)
PA=addr
Physical address that missed(hexadecimal with leading 0x)
WAY=val
Cache way(decimal)
4.6 D-Cache hit event
Format :full
DC_HIT_(R|W),CY=cyclenum,TH=tnum,PC=addr,VA=addr, PA=addr,WAY=val
where:(R|W)
Access: R=Read data, W=Write data
CY=cyclenum
Cycle number(decimal)
TH=tnum
Hardware thread number(decimal)
PC=addr
Instruction address when hit occurred(hexadecimal with leading 0x)
VA=addr
Virtual address that hit(hexadecimal with leading 0x)
PA=addr
Physical address that hit(hexadecimal with leading 0x)
WAY=val
Cache way(decimal)
4.7 I-TLB write event
Format :full
ITLB_WRITE,CY=cyclenum,TH=tnum,VA=addr,IDX=val where:
CY=cyclenum
Cycle number(decimal)
TH=tnum
Hardware thread number(decimal)
VA=addr
Virtual address written(hexadecimal with leading 0x)
IDX=val
TLB index written(decimal)
4.8 I-TLB miss event
Format :full
ITLB_MISS,CY=cyclenum,TH=tnum,VA=addr where:
CY=cyclenum
Cycle number(decimal)
TH=tnum
Hardware thread number(decimal)
VA=addr
Virtual address that missed(hexadecimal with leading 0x)
4.9 D-TLB write event
Format :full
DTLB_WRITE,CY=cyclenum,TH=tnum,VA=addr,IDX=val where:
CY=cyclenum
Cycle number(decimal)
TH=tnum
Hardware thread number(decimal)
VA=addr
Virtual address written(hexadecimal with leading 0x)
IDX=val
TLB index written(decimal)
4.10 D-TLB miss event
Format :full
DTLB_MISS,CY=cyclenum,TH=tnum,VA=addr where:
CY=cyclenum
Cycle number(decimal)
TH=tnum
Hardware thread number(decimal)
VA=addr
Virtual address that missed(hexadecimal with leading 0x)
Format :full
INTT,CY=cyclenum,TH=tnum,INT=intnum,ELR=addr,DPC=addr where:
CY=cyclenum
Cycle number(decimal)
TH=tnum
Hardware thread number(decimal)
INT=intnum
Interrupt number(decimal)
ELR=addr
Exception link register-return virtual address(hexadecimal with leading 0x)
DPC=addr
Destination instruction address – inthandler(hexadecimal with leading 0x)
4.13 RTE event
Format :full
RTE,CY=cyclenum,TH=tnum,PC=addr,DPC=addr where:
CY=cyclenum
Cycle number(decimal)
TH=tnum
Hardware thread number(decimal)
PC=addr
RTE instruction address(hexadecimal with leading 0x)
DPC=addr
Destination instruction address(hexadecimal with leading 0x)
4.14 Call event
Format :full
CALL,CY=cyclenum,TH=tnum,PC=addr,DPC=addr where:
CY=cyclenum
Cycle number(decimal)
TH=tnum
Hardware thread number(decimal)
PC=addr
Call instruction address(hexadecimal with leading 0x)
DPC=addr
Destination instruction address(hexadecimal with leading 0x)
4.15 Software thread switch event
Format :full
SWTS,CY=cyclenum,TH=tnum,ASID=val,SWT=swtnum,NAME=string where:
CY=cyclenum
Cycle number(decimal)
TH=tnum
Hardware thread number(decimal)
ASID=val
Address space ID(hexadecimal with leading 0x)
SWT=swtnum
Software thread number(hexadecimal with leading 0x)
NAME=string
Software thread name(double-quoted string)
4.16 Trap event
Format :full
TRAP,CY=cyclenum,TH=tnum,TRAP=trapnum,ELR=addr,DPC=addr where:
CY=cyclenum
Cycle number(decimal)
TH=tnum
Hardware thread number(decimal)
TRAP=trapnum
Trap number(decimal)
ELR=addr
Exception link register-return virtual address(hexadecimal with leading 0x)
DPC=addr
Destination instruction address – trap handler(hexadecimal with leading 0x)
4.17 Miscellaneous change of flow event
Format :full
COF,CY=cyclenum,TH=tnum,PC=addr,DPC=addr, TYPE=(ENDLOOP0|ENDLOOP1|JUMPR_R31|JUMPR|JUMP|JUMPNEW)
where:
CY=cyclenum
Cycle number(decimal)
TH=tnum
Hardware thread number(decimal)
PC=addr
Change of flow instruction address(hexadecimal with leading 0x)
DPC=addr
Destination instruction address(hexadecimal with leading 0x)
TYPE=(ENDLOOP0|ENDLOOP1|JUMPR_R31|JUMPR|JUMP|JUMPNEW) Type of flow change instruction:
❒ ENDLOOP0 — End of hardware loop 0 instruction sequence
❒ ENDLOOP1 — End of hardware loop 1 instruction sequence
❒ JUMPR_R31 — Function call return(typically)
❒ JUMPR — Direct jump through register
❒ JUMP — Direct jump to address
❒ JUMPNEW — Direct jump to address based on new predicate