vsim选项 option

modelsim Vsim选项整理

1. vsim指令载入一个设计到仿真器，语句格式：

Vsim [option] +TESTNAME=[测试名] [逻辑库.tb文件]

2. 常用选项：

# 常用
-c # 使vsim运行在命令行模式，不启动图形界面，节省时间
-novopt # 不采用vopt优化，常和+acc配合使用
-l <logfile> # 输出仿真的log文件
-do <dofile> # 开始仿真后运行tcl脚本（控制文件）
-L # 加载所需要的仿真库文件
-sv_seed 0 随机种子
 
# 其它
-t # <ps or ns> 定义仿真时间精度
-g|G<name=value> # 设置VHDL的generic参数值
-quiet # 关闭loading的信息
-coverage # 收集覆盖率信息 
-classdebug 更多类调试功能
-solvefaileddebug 随机化失败更多信息

3. 例子

vsim -c -l vsim.log -do ./DemoDo.do -L ./work work.foo # 命令行模式，输出日志到vsim.log，开始仿真后运行DemoDo.do脚本文件，指定逻辑库work，work.foo是仿真的top level module

4. vsim之外的其他questa常用指令

vlog # 编译
vlib # 建立一个新的工作库/逻辑库
vmap # 映射逻辑库名到制定的目录
add wave # 将信号加入波形
run # 执行仿真（默认执行100ns，-all 执行到结束）

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vsim

The vsim command is used to invoke the VSIM simulator, or to view the results of a previous simulation run (when invoked with the -view switch). You can specify a configuration, an entity/architecture pair, or a module for simulation. If a configuration is specified, it is invalid to specify an architecture. With no options, vsim brings up the Load Design dialog box, allowing you to specify the design and options; the Load Design dialog box will not be presented if you specify any options. During elaboration vsim determines if the source has been modified since the last compile.

To manually interrupt design elaboration use the Break key or (while the mouse cursor is located in the window that invoked vsim if you are running UNIX).

The vsim command may also be invoked from the command line within ModelSim with most of the options shown below (all except the vsim -c and -restore options).

Syntax

vsim
[-assertfile ] [-c] [-coverage]
[-do “<command_string>” | <macro_file_name>] [-f ]
[-g= …] [-G= …] [-gui]
[-help] [-i] [-installcolormap] [-keeploaded] [-keeploadedrestart]
[-keepstdout] [-l ] [-lib [<library_name>]] [<license_option>]
[-multisource_delay min | max | latest] [-nocompress] [+no_notifier] [+no_tchk_msg] [+notimingchecks] [-quiet] [-restore ]
[-sdfmin | -sdftyp | -sdfmax [=]<sdf_filename>]
[-sdfnoerror] [-sdfnowarn] [+sdf_verbose] [-t []<time_unit>]
[tag ] [-title

[-absentisempty] [-foreign ] [-nocollapse] [-nofileshare]
[-noglitch] [+no_glitch_msg] [std_input ] [std_output ] [-strictvital] [-vcdread ]
[-vital2.2b]

[+alt_path_delays] [extend_tcheck_data_limit ] [extend_tcheck_ref_limit ] [-hazards] [+int_delays]
[-L <library_name> …] [-Lf <library_name> …] [+maxdelays] [+mindelays] [+multisource_int_delays] [+no_cancelled_e_msg] [+no_neg_tchk] [+no_path_edge] [+no_pulse_msg] [+nosdferror] [+no_show_cancelled_e] [+nosdfwarn] [+nospecify] [+nowarn] [+ntc_warn]
[-pli “”] [+] [+pulse_e/] [+pulse_e_style_ondetect] [+pulse_e_style_onevent]
[+pulse_int_e/] [+pulse_int_r/] [+pulse_r/] [+show_cancelled_e] [+sdf_nocheck_celltype] [+transport_int_delays] [+transport_path_delays] [+typdelays] [-v2k_int_delays]

[<library_name>.<design_unit>]

VSIM arguments are grouped alphabetically by language:

Arguments, VHDL and Verilog
Arguments, VHDL
Arguments, Verilog
Arguments, design-unit

Arguments, VHDL and Verilog

-assertfile
Designates an alternative file for recording assertion messages. Optional. By default assertion messages are output to the file specified by the TranscriptFile variable in the modelsim.ini file (see “Creating a transcript file” ).

-c
Specifies that the simulator is to be run in command line mode. Optional. Also see “Running command-line and batch-mode simulations” for more information.

-coverage
Allows line number execution statistics to be kept by the simulator. By default no statistics are kept. This switch must be specified during command-line invocation of the simulator in order to use the various coverage commands: coverage clear, coverage reload, and coverage report. Also see Code Coverage chapter for more information. Optional.

-do “<command_string>” | <macro_file_name>
Instructs VSIM to use the command(s) specified by <command_string> or the macro file named by <macro_file_name> rather than the startup file specified in the .ini file, if any. Optional.

-f
Specifies a file with more command line arguments. Allows complex arguments to be reused without retyping. Optional.

-g= …
Assigns a value to all specified VHDL generics and Verilog parameters that have not received explicit values in generic maps, instantiations, or via def params (such as top-level generics/parameters and generics/parameters that would otherwise receive their default values). Optional. Note there is no space between -g and =.

Name is the name of the generic/parameter, exactly as it appears in the VHDL source (case is ignored). Value is an appropriate value for the declared data type of a VHDL generic or any legal value for a Verilog parameter. Make sure the Value you specify for a VHDL generic is appropriate for VHDL declared data types. VHDL type mismatches will cause the specification to be ignored (including no error messages).

No spaces are allowed anywhere in the specification, except within quotes when specifying a string value. Multiple -g options are allowed, one for each generic/parameter.

Name may be prefixed with a relative or absolute hierarchical path to select generics in an instance-specific manner. For example,

Specifying -g/top/u1/tpd=20ns on the command line would affect only the tpd generic on the /top/u1 instance, assigning it a value of 20ns.

Specifying -gu1/tpd=20ns affects the tpd generic on all instances named u1.

Specifying -gtpd=20ns affects all generics named tpd.

If more than one -g option selects a given generic the most explicit specification takes precedence. For example,

vsim -g/top/ram/u1/tpd_hl=10ns -gtpd_hl=15ns top
This command sets tpd_hl to 10ns for the /top/ram/u1 instance. However, all other tpd_hl generics on other instances will be set to 15ns.

Limitation: In general, generics/parameters of composite type (arrays and records) cannot be set from the command line. However, you can set string arrays, std_logic vectors, and bit vectors if they can be set using a quoted string. For example,

-gstrgen=“This is a string”
-gslv=“01001110”
The quotation marks must make it into vsim as part of the string because the type of the value must be determinable outside of any context. Therefore, when entering this command from a shell, put a forward tick around the string. For example:

-gstrgen=‘“This is a string”’
If working within the ModelSim GUI, you would enter the command as follows:

{-gstrgen=“This is a string”}

Note: When you compile Verilog code with -fast (see vlog), all parameter values are set at compile time. Therefore, the -g option has no effect on these parameters.
-G= …
Same as -g (see above) except that it will also override generics/parameters that received explicit values in generic maps, instantiations, or via def params. Optional. Note there is no space between -G and =.

-gui
Starts the ModelSim GUI without loading a design. Optional.

-help
Displays the command’s options and arguments. Optional.

-i
Specifies that the simulator is to be run in interactive mode. Optional. If used, must be the first argument.

-installcolormap
For UNIX only. Causes vsim to use its own colormap so as not to hog all the colors on the display. This is similar to the -install switch on Netscape. Optional.

-keeploaded
Prevents the simulator from unloading/reloading any FLI/PLI/VPI shared libraries when it restarts or loads a new design. Optional. The shared libraries will remain loaded at their current positions. User application code in the shared libraries must reset its internal state during a restart in order for this to work effectively.

-keeploadedrestart
Prevents the simulator from unloading/reloading any FLI/PLI/VPI shared libraries during a restart. Optional. The shared libraries will remain loaded at their current positions. User application code in the shared libraries must reset its internal state during a restart in order for this to work effectively.

We recommend using this option if you’ll be doing warm restores after a restart and the user application code has set callbacks in the simulator. Otherwise, the callback function pointers might not be valid if the shared library is loaded into a new position.

-keepstdout
For use with foreign programs. Instructs the simulator to not redirect the stdout stream to the Main window. Optional.

-l
Saves the contents of the “Main window” transcript to . Optional. Default is transcript. Can also be specified using the .ini (see “Creating a transcript file” ) file or the .tcl preference file.

-lib [<library_name>]
This argument has been replaced by the .<design_unit> argument. Specifies the name of the library in which the design unit resides. Optional. If the optional library specification is omitted the work library is used.

<license_option>
Restricts the search of the license manager. Optional. Use one of the following options.

<license_option>	Description
-lic_nomgc	exclude any MGC licenses from the search
-lic_nomti	exclude any MTI licenses from the search
-lic_noqueue	do not wait in queue when license is unavailable
-lic_plus	search only for ModelSim SE/PLUS licenses
-lic_vhdl	search only for ModelSim SE/VHDL licenses
-lic_viewsim	accept a simulator license rather than be queued for a viewer licens
-lic_vlog	searches only for ModelSim SE/VLOG licenses

The options may also be specified with the License variable in the modelsim.ini file. Note that settings made from the command line are additive to options set in the License variable. For example, if you set the License variable to nomgc and use the lic_plus option from the command line, vsim will search only for MTI SE/PLUS licenses.

-multisource_delay min | max | latest
Controls the handling of multiple PORT or INTERCONNECT constructs that terminate at the same port. Optional. By default, the Module Input Port Delay (MIPD) is set to the max value encountered in the SDF file. Alternatively, you may choose the min or latest of the values. If you have a Verilog design and want to model multiple interconnect paths independently, use the +multisource_int_delays switch (see “Arguments, Verilog” ).

-nocompress
Causes VSIM to create uncompressed checkpoint files. Optional. This option must be used with the -restore option (below) to restore a simulation from an uncompressed checkpoint file. This option may also be specified with the CheckpointCompressMode variable in the modelsim.ini file.

+no_notifier
Timing messages will be issued for timing constraint violations, but X propagation will be prevented for these violations. Optional.

+no_tchk_msg
Disables timing constraint error messages. Optional.

+notimingchecks
Disables Verilog and VITAL timing checks for faster simulation. Optional. By default, Verilog timing check system tasks ($setup, $hold,…) in specify blocks are enabled. For VITAL, the timing check default is controlled by the ASIC or FPGA vendor, but most default to enabled.

-quiet
Disable ‘loading’ messages during batch-mode simulation. Optional.

-restore
Specifies that VSIM is to restore a simulation saved with the checkpoint command. Optional. Use the -nocompress switch (above) if compression was turned off when the checkpoint command was used or if VSIM was initially invoked with nocompress. See additional discussion in “How to use checkpoint/restore” ; nocompress is also an option of the restore command.

Note: You must restore vsim under the same environment in which you did the checkpoint. This means not only the same type of machine and OS and at least the same memory size, but also the same vsim environment such as GUI vs. command line mode.
-sdfmin | -sdftyp | -sdfmax [=]<sdf_filename>
Annotates VITAL or Verilog cells in the specified SDF file (a Standard Delay Format file) with minimum, typical, or maximum timing. Optional. The use of [=] with <sdf_filename> is also optional; it is used when the backannotation is not being done at the top level. See “Specifying SDF files for simulation” .

-sdfnoerror
Errors issued by the SDF annotator while loading the design prevent the simulation from continuing, whereas warnings do not. Changes SDF errors to warnings so that the simulation can continue. Optional.

-sdfnowarn
Disables warnings from the SDF reader. Optional.

See VHDL Simulation chapter for an additional discussion of SDF.

+sdf_verbose
Turns on the verbose mode during SDF annotation. The Main window provides detailed warnings and summaries of the current annotation. Optional.

-t []<time_unit>
Specifies the simulation time resolution. Optional; if omitted, the value specified for the Resolution variable in the modelsim.ini file will be used. If Verilog `timescale directives are found, the minimum time precision will be used. <time_unit> must be one of the following:

fs, ps, ns, us, ms, sec

The default is 1ns; the optional may be 1, 10 or 100. Note that there is no space between the multiplier and the unit (i.e., 10fs, not 10 fs).

Once you’ve begun simulation, you can determine the current simulator resolution by invoking the report command with the simulator state option.

tag
Specifies a string tag to append to foreign trace filenames. Optional; used with the trace_foreign option. Used when running multiple traces in the same directory. See “Invoking a trace” .

-title

-trace_foreign
Creates two kinds of foreign interface traces: a log of what functions were called, with the value of the arguments, and the results returned; and a set of C-language files to replay what the foreign interface side did.

The purpose of the logfile is to aid the debugging of your FLI and/or PLI code. The primary purpose of the replay facility is to send the replay file to MTI support for debugging co-simulation problems, or debugging problems for which it is impractical to send the FLI/ PLI code. See “Invoking a trace” for more information.

-vcdstim
Resimulates a design from a VCD file. Optional. The VCD file must have been created in a previous simulation using the vcd dumpports command. See “Resimulating a design from a VCD file” for more information.

-version
Returns the version of the simulator as used by the licensing tools, such as “Model Technology ModelSim SE vsim 5.5 Simulator 2000.01 Jan 28 2000”.

-view [<dataset_name>=]<WLF_filename>
Specifies a wave log format (WLF) file for vsim to read. Allows you to use VSIM to view the results from an earlier simulation. The Structure, Signals, Wave, and List windows can be opened to look at the results stored in the WLF file (other ModelSim windows will not show any information when you are viewing a dataset). See additional discussion in “Examples” .

vsim -view test=sim2.wlf
-wlf
Specifies the name of the wave log format (WLF) file to create. The default is vsim.wlf. Optional.

-wlfcompress
Creates compressed WLF files. Default. Use -wlfnocompress to turn off compression.

-wlfnocompress
Causes VSIM to create uncompressed WLF files. Optional. Beginning with version 5.5, WLF files are compressed by default in order to reduce file size. This may slow simulation speed by one to two percent. You may want to disable compression to speed up simulation or if you are experiencing problems with faulty data in the resulting WLF file. This option may also be specified with the WLFCompress variable in the modelsim.ini file.

-wlfslim
Specifies a size restriction in megabytes for the event portion of the WLF file. Optional. The default is infinite size (0). The must be an integer.

Note that a WLF file contains event, header, and symbol portions. The size restriction is placed on the event portion only. When ModelSim exits, the entire header and symbol portion of the WLF file is written. Consequently, the resulting file will be larger than the size specified with -wlfslim.

If used in conjunction with -wlftlim, the more restrictive of the limits will take effect.

This option may also be specified with the WLFSizeLimit variable in the modelsim.ini file.

-wlftlim
Specifies the duration of simulation time for WLF file recording. Optional. The default is infinite time (0). The is an integer of simulation time at the current resolution; you can optionally specify the resolution if you place curly braces around the specification. For example,

{5000 ns}
sets the duration at nanoseconds regardless of the current simulator resolution.

The time range begins at current simulation time and moves back in simulation time for the specified duration. For example,

vsim -wlftlim 5000
writes at least the last 5000ns of the current simulation to the WLF file (the current simulation resolution in this case is ns).

If used in conjunction with -wlfslim, the more restrictive of the limits will take effect.

This option may also be specified with the WLFTimeLimit variable in the modelsim.ini file.

Note: The -wlfslim and -wlftlim switches were designed to help users limit WLF file sizes for long or heavily logged simulations. When small values are used for these switches, the values may be overridden by the internal granularity limits of the WLF file format.

Arguments, VHDL

-absentisempty
Causes VHDL files opened for read that target non-existent files to be treated as empty, rather than ModelSim issuing fatal error messages. Optional.

-foreign
Specifies the foreign module to load. Optional. is a quoted string consisting of the name of a C function and a path to a shared library. For example,

vsim -foreign “c_init for.sl”
You can load up to ten foreign modules. Syntax for the attribute is further described in the Introduction chapter of the ModelSim FLI Reference.

-nocollapse
Disables the optimization of internal port map connections. Optional.

-nofileshare
By default ModelSim shares a file descriptor for all VHDL files opened for write or append that have identical names. The -nofileshare switch turns off file descriptor sharing. Optional.

-noglitch
Disables VITAL glitch generation. Optional.

See VHDL Simulation chapter for additional discussion of VITAL.

+no_glitch_msg
Disable VITAL glitch error messages. Optional.

std_input
Specifies the file to use for the VHDL TextIO STD_INPUT file. Optional.

std_output
Specifies the file to use for the VHDL TextIO STD_OUTPUT file. Optional.

-strictvital
Exactly match the VITAL package ordering for messages and delta cycles. Optional. Useful for eliminating delta cycle differences caused by optimizations not addressed in the VITAL LRM. Using this argument negatively impacts simulator performance.

-vcdread
Simulates the VHDL top-level design from the specified VCD file. Optional. This argument is included for backwards compatibility. Resimulations in ModelSim versions 5.5c and newer should use the -vcdstim argument. See “Resimulating a design from a VCD file” for more details.

-vital2.2b
Selects SDF mapping for VITAL 2.2b (default is VITAL 95). Optional.

Arguments, Verilog

+alt_path_delays
Use the current output value instead of the pending value when selecting inertial specify path output delay. Optional.

extend_tcheck_data_limit
extend_tcheck_ref_limit
Causes a one-time extension of of qualifying limits in an attempt to provide a delay net delay solution prior to any limit zeroing. Optional. is the maximum percent of limit relaxation. A limit qualifies if it bounds a violation region which does not overlap a related violation region.

For example,

$setuphold( posedge clk, posedge d, 45, 70, notifier,dclk,dd);
$setuphold( posedge clk, negedge d, 216, -68, notifier,dclk,dd);
are the same check type and have the same delay nets and thus are related.

The delay net delay analysis in this case does not provide a solution as the required delay between d and dd of 68 for the negative hold could cause a non-violating posedge d transition to be delayed on dd so that it could arrive after dclk for functional evaluation. By default the -68 hold limit is set pessimistically to 0 to insure the correct functional evaluation.

The other option is to use -extend_tcheck_data_limit to change the data limit of -68 to 44 (a 21 percent adjustment) or -extend_tcheck_ref_limit to change the reference limit of 45 to 69 (a 16 percent adjustment).

-hazards
Enables hazard checking in Verilog modules. Optional.

+int_delays
Optimizes annotation of interconnect delays for designs that have been compiled using fast (see vlog command). Optional. This argument causes VSIM to insert “placeholder” delay elements at optimized cell inputs, resulting in faster backannotation of interconnect delay from an SDF file.

-L <library_name> …
Specifies the library to search for design units instantiated from Verilog. If multiple libraries are specified, each must be preceded by the -L option.

-Lf <library_name> …
Same as -L but libraries are searched before `uselib directives. Optional.

+maxdelays
Selects maximum timing from Verilog min:typ:max expressions. Optional.

+mindelays
Selects minimum timing from Verilog min:typ:max expressions. Optional.

+multisource_int_delays
Enables multisource interconnect delay with pulse handling and transport delay behavior. Optional. Use this switch when you have interconnect data in your SDF file and you want the delay on each interconnect path modeled independently.

+no_cancelled_e_msg
Disables warning messages for negative pulses on specify path delays. Optional.

+no_neg_tchk
Sets negative timing check limits to zero. Optional.

+no_path_edge
Ignores the input edge specification on path delays. Optional.

+no_pulse_msg
Disables path pulse error warning messages. Optional.

+nosdferror
Errors issued by the SDF annotator while loading the design prevent the simulation from continuing, whereas warnings do not. Changes SDF errors to warnings so that the simulation can continue. Optional.

+no_show_cancelled_e
Filters negative pulses on specify path delays so they don’t show up on the output. Default. Use +show_cancelled_e to drive a pulse error state.

+nosdfwarn
Disables warnings from the SDF annotator. Optional.

+nospecify
Disables specify path delays and timing checks. Optional.

+nowarn
Disables warning messages in the category specified by . Optional. Warnings that can be disabled include the name in square brackets in the warning message. For example, the code for too few port connections is TFMPC, so use +nowarnTFMPC to disable them.

+ntc_warn
This option enables warning messages from the negative timing constraint algorithm. This algorithm attempts to find a set of delays for the timing check delayed net arguments such that all negative limits can be converted to non-negative limits with respect to the delayed nets. If there is no solution for this set of limits, then the algorithm sets one of the negative limits to zero and recalculates the delays. This process is repeated until a solution is found. A warning message is issued for each negative limit set to zero. Optional. By default, these warnings are disabled.

-pli “”
Loads a space-separated list of PLI shared objects. Optional. The list must be quoted if it contains more than one object. This is an alternative to specifying PLI objects in the Veriuser entry in the modelsim.ini file, see “Preference variables located in INI files” . You can use environment variables as part of the path.

+
Arguments preceded with “+” are accessible by the Verilog PLI routine mc_scan_plusargs. Optional.

+pulse_e/
Sets module path pulse error limit as percentage of path delay. Optional.

+pulse_e_style_ondetect
This option selects the “on detect” style of propagating pulse errors (see +pulse_e). A pulse error propagates to the output as an X, and the “on detect” style is to schedule the X immediately, as soon as it has been detected that a pulse error has occurred. The “on event” style is the default for propagating pulse errors (see +pulse_e_style_onevent).

+pulse_e_style_onevent
This option selects the “on event” style of propagating pulse errors (see +pulse_e). A pulse error propagates to the output as an X, and the “on event” style is to schedule the X to occur at the same time and for the same duration that the pulse would have occurred if it had propagated through normally. The “on event” style is the default for propagating pulse errors.

+pulse_int_e/
Sets the interconnect path pulse error limit as percentage of path delay. Optional. Used in conjunction with +multisource_int_delays (see above).

+pulse_int_r/
Sets the interconnect path pulse rejection limit as percentage of path delay. Optional. Used in conjunction with +multisource_int_delays (see above).

+pulse_r/
Sets module path pulse rejection limit as a percentage of path delay. Optional.

+show_cancelled_e
Drives a pulse error state (‘X’) for the duration of a negative pulse on a specify path delay. Optional.

+sdf_nocheck_celltype
By default, the SDF annotator checks that the CELLTYPE name in the SDF file matches the module or primitive name for the CELL instance. It is an error if the names do not match. The +sdf_nocheck_celltype option disables this error check.

+transport_int_delays
By default, interconnect delays operate in inertial mode (pulses smaller than the delay are filtered). The +transport_int_delays option selects transport mode with pulse control for single-source nets (one interconnect path). In transport mode, narrow pulses are propagated through interconnect delays. This option works independently from +multisource_int_delays. Optional.

+transport_path_delays
By default, path delays operate in inertial mode (pulses smaller than the delay are filtered). The +transport_path_delays option selects transport mode for path delays. In transport mode, narrow pulses are propagated through path delays. Note that this option affects path delays only, and not primitives. Primitives always operate in inertial delay mode. Optional.

+typdelays
Selects typical timing from Verilog min:typ:max expressions. Optional. Default.

-v2k_int_delays
Causes interconnect delay to be visible at the load module port. Optional. If you have $sdf_annotate() calls in your design that are not getting executed, add the Verilog task $sdf_done() after your last $sdf_annotate() to remove any zero-delay MIPDs that may have been created. May be used in tandem with +multisource_int_delays argument (see above).

Arguments, design-unit

The following library/designunit arguments may be used with vsim. If no design-unit specification is made, VSIM will open the Load a Design dialog box. Multiple design units may be specified for Verilog modules and mixed VHDL/Verilog configurations.

<library_name>.<design_unit>
Specifies a library and associated design unit; multiple library/design unit specifications can be made. Optional. If no library is specified, the work library is used.

The <design_unit> may be one of the following:

Specifies the VHDL configuration to simulate.

…

Specifies the name of one or more top-level Verilog modules to be simulated. Optional.

[()]

Specifies the name of the top-level VHDL entity to be simulated. Optional. The entity may have an architecture optionally specified; if omitted the last architecture compiled for the specified entity is simulated. An entity is not valid if a configuration is specified.

Note: Most UNIX shells require arguments containing () to be single-quoted to prevent special parsing by the shell. See the examples below.

Examples

vsim -gedge='"low high"' -gVCC=4.75 cpu
Invokes VSIM on the entity cpu and assigns values to the generic parameters edge and VCC. If working within the ModelSim GUI, you would enter the command as follows:

vsim {-gedge="low high"} -gVCC=4.75 cpu
vsim -view test=sim2.wlf
Instructs ModelSim to view the results of a previous simulation run stored in the WLF file sim2.wlf. The simulation is displayed as a dataset named “test”. Use the -wlf option to specify the name of the WLF file to create if you plan to create many files for later viewing. For example:

vsim -wlf my_design.i01 my_asic structure 
vsim -wlf my_design.i02 my_asic structure  

vsim -sdfmin /top/u1=sdf1

Annotates instance /top/u1 using the minimum timing from the SDF file sdf1.

Use multiple switches to annotate multiple instances:

vsim -sdfmin /top/u1=sdf1 -sdfmin /top/u2=sdf2 top

vsim 'mylib.top(only)' gatelib.cache_set
This example searches the libraries mylib for top(only) and gatelib for cache_set. If the design units are not found, the search continues to the work library. Specification of the architecture (only) is optional.