HDLBits Fsm1

1、这个题刚开始确实没想出来咋写。两个状态切换倒是知道。

2、输出如果是a状态输出0.b状态输出1。输入的话如果输入是0就切换状态，输入是1就维持原状态。

完整代码如下： 

module top_module(
    input clk,
    input areset,    // Asynchronous reset to state B
    input in,
    output out);//  

    parameter A=0, B=1; //定义两个状态值
    reg state, next_state;//定义两个状态名称

    always @(*) begin    // This is a combinational always block
        // State transition logic变换状态
        if(state==A)
            next_state=(in)?state:B;
        if(state==B)
            next_state=(in)?state:A;
        
    end

    always @(posedge clk, posedge areset) begin    // This is a sequential always block
        // State flip-flops with asynchronous reset
        if(areset)begin
            state<=B;
        end
        else begin
            //out <= (next_state == A)?0:1;
            state<=next_state;//将下一个状态赋值给当前状态
        end
        
        
    end

    // Output logic
    assign out = (state == A)?0:1;

endmodule