用verilog实现Multiplexer

Mux2to1：

module top_module (
	input a,
	input b,
	input sel,
	output out
);

	assign out = sel ? b : a;	
endmodule

Mux9to1v:

odule top_module (
	input [15:0] a,
	input [15:0] b,
	input [15:0] c,
	input [15:0] d,
	input [15:0] e,
	input [15:0] f,
	input [15:0] g,
	input [15:0] h,
	input [15:0] i,
	input [3:0] sel,
	output logic [15:0] out
);	

		case (sel)
			4'h0: out = a;
			4'h1: out = b;
			4'h2: out = c;
			4'h3: out = d;
			4'h4: out = e;
			4'h5: out = f;
			4'h6: out = g;
			4'h7: out = h;
			4'h8: out = i;
		endcase
	end
	
endmodule

**Mux256to1:**
module top_module (
	input [255:0] in,
	input [7:0] sel,
	output  out
);

	assign out = in[sel];
	
endmodule

Mux256to1v:

module top_module (
	input [1023:0] in,
	input [7:0] sel,
	output [3:0] out
);

	
	assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};

	// Alternatively, "indexed vector part select" works better, but has an unfamiliar syntax:
	// assign out = in[sel*4 +: 4];		// Select starting at index "sel*4", then select a total width of 4 bits with increasing (+:) index number.
	// assign out = in[sel*4+3 -: 4];	// Select starting at index "sel*4+3", then select a total width of 4 bits with decreasing (-:) index number.
	// Note: The width (4 in this case) must be constant.

endmodule

详情见HDLbits Multiplexer.