Fsm serial

方法1：这个是基于两段式，到后边例题的时候不好修改。

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
    parameter idle=0,start=1,data1=2,data2=3,data3=4,data4=5,
    data5=6,data6=7,data7=8,data8=9,stop=10,error=11;
    reg [3:0]c_s,n_s;
    always @(posedge clk)
        begin
            if(reset)
                c_s<=idle;
            else
                c_s<=n_s;
        end
    always @(*)
        begin
            if(~reset)
                begin
            case(c_s)
            	idle:n_s=~in?start:idle;
                start:n_s=data1;
                data1:n_s=data2;
                data2:n_s=data3;
                data3:n_s=data4;
                data4:n_s=data5;
                data5:n_s=data6;
                data6:n_s=data7;
                data7:n_s=data8;
                data8:n_s=in?stop:error;
                error:n_s=in?idle:error;
                stop:n_s=in?idle:start;
                default:n_s=idle;
            endcase
                end
            else
                n_s=idle;
        end
    assign done=(c_s==stop)?1:0;           
endmodule

方法2：这个是基于三段式

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
    parameter 
    idle=0,
    start=1,
    data=2,
    stop=3,
    error=4;
    reg [2:0]state,n_state;
    reg [3:0]cnt;
    always @(posedge clk) begin
        if(reset)
            state<=idle;
        else 
            state<=n_state; 
    end
    always @(*) begin
    	n_state=idle;
        case(state)
            idle:n_state=(~in)?start:idle;
            start:n_state=data;
            data:n_state=(cnt==8)?(in?stop:error):data;
            error:n_state=(~in)?error:idle;
            stop:n_state=(in)?idle:start;
            default:;
        endcase
    end
    //输出
    always @(posedge clk)begin
        if(reset) begin
            done<=0;
            cnt<=0;
        end
        else
            case(n_state)
            	data:begin
                   done<=0;
                   cnt<=cnt+1;
                end
                stop:begin
                   done<=1;
                    cnt<=0;
                end
            	default:begin
                   done<=0;
                    cnt<=0;
                end
            endcase       
    end  
endmodule