HDLbits-状态机05/06-Fsm3comb

 

 

module top_module(
    input in,
    input [1:0] state,
    output [1:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    always@(*)
    case(state)
        A:
            if(in)
                next_state=B;
       		else
           		next_state=A;
        B:
            if(in)
                next_state=B;
       		else
           		next_state=C;
        C:
            if(in)
                next_state=D;
       		else
           		next_state=A;
       D:
            if(in)
                next_state=B;
       		else
           		next_state=C;
         
    endcase// State transition logic: next_state = f(state, in)
   always@(*)
     case(state)
        A:
           out=0;
        B:
           out=0;
        C:
           out=0;
        D:
           out=1;
     endcase // Output logic:  out = f(state) for a Moore state machine

endmodule

 

 

module top_module(
    input in,
    input [3:0] state,
    output [3:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

    // State transition logic: Derive an equation for each state flip-flop.
    assign next_state[A] = state[A]&(~in)|state[C]&(~in);
    assign next_state[B] = state[A]&in|state[B]&in|state[D]∈
    assign next_state[C] = state[B]&(~in)|state[D]&(~in);
    assign next_state[D] = state[C]∈

    // Output logic: 
    assign out = state[D]==1;

endmodule

 

写成 assign out=state==D；会出错