使用3-8译码器实现全减器（Verilog详细解析设计篇）

        使用3-8译码器和必要的逻辑门实现全减器，全减器接口图如下，A是被减数，B是减数，Ci是来自低位的借位，D是差，Co是向高位的借位。

 

       

        逻辑真值表中，输入信号的每种组合对应着一个输出端的高电平信号 ，即输出端为高电平(1) 时认为该输出端有输出信号。当然，根据有需要也可以定义输出端为低电平(0) 时认为该输出端有输入信号，此时称输出端低电平有效。 

        要实现次功能，首先要懂得3-8译码器的工作原理，全减器的工作原理：

一.3-8译码器工作原理

1. 3-8译码器真值表：

2. 表达式：

                                     

3. 代码： 

module decoder_38(
   input             E      ,
   input             A0     ,
   input             A1     ,
   input             A2     ,
   
   output reg       Y0n    ,  
   output reg       Y1n    , 
   output reg       Y2n    , 
   output reg       Y3n    , 
   output reg       Y4n    , 
   output reg       Y5n    , 
   output reg       Y6n    , 
   output reg       Y7n    
);

always @(*)begin
   if(!E)begin
      Y0n = 1'b1;
      Y1n = 1'b1;
      Y2n = 1'b1;
      Y3n = 1'b1;
      Y4n = 1'b1;
      Y5n = 1'b1;
      Y6n = 1'b1;
      Y7n = 1'b1;
   end  
   else begin
      case({A2,A1,A0})
         3'b000 : begin
                     Y0n = 1'b1; Y1n = 1'b0; Y2n = 1'b0; Y3n = 1'b0; 
                     Y4n = 1'b0; Y5n = 1'b0; Y6n = 1'b0; Y7n = 1'b0;
                  end 
         3'b001 : begin
                     Y0n = 1'b0; Y1n = 1'b1; Y2n = 1'b0; Y3n = 1'b0; 
                     Y4n = 1'b0; Y5n = 1'b0; Y6n = 1'b0; Y7n = 1'b0;
                  end 
         3'b010 : begin
                     Y0n = 1'b0; Y1n = 1'b0; Y2n = 1'b1; Y3n = 1'b0; 
                     Y4n = 1'b0; Y5n = 1'b0; Y6n = 1'b0; Y7n = 1'b0;
                  end 
         3'b011 : begin
                     Y0n = 1'b0; Y1n = 1'b0; Y2n = 1'b0; Y3n = 1'b1; 
                     Y4n = 1'b0; Y5n = 1'b0; Y6n = 1'b0; Y7n = 1'b0;
                  end 
         3'b100 : begin
                     Y0n = 1'b0; Y1n = 1'b0; Y2n = 1'b0; Y3n = 1'b0; 
                     Y4n = 1'b1; Y5n = 1'b0; Y6n = 1'b0; Y7n = 1'b0;
                  end 
         3'b101 : begin
                     Y0n = 1'b0; Y1n = 1'b0; Y2n = 1'b0; Y3n = 1'b0; 
                     Y4n = 1'b0; Y5n = 1'b1; Y6n = 1'b0; Y7n = 1'b0;
                  end 
         3'b110 : begin
                     Y0n = 1'b0; Y1n = 1'b0; Y2n = 1'b0; Y3n = 1'b0; 
                     Y4n = 1'b0; Y5n = 1'b0; Y6n = 1'b1; Y7n = 1'b0;
                  end 
         3'b111 : begin
                     Y0n = 1'b0; Y1n = 1'b0; Y2n = 1'b0; Y3n = 1'b0; 
                     Y4n = 1'b0; Y5n = 1'b0; Y6n = 1'b0; Y7n = 1'b1;
                  end 
         default: begin
                     Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
                     Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;
                  end
      endcase  
   end 
end    
     
endmodule

 

 二.全减器工作原理

  1.  全减器真值表

输入			输出	输出
C_i	A	B	D	C_o
0	0	0	0	0
0	0	1	1	1
0	1	0	1	0
0	1	1	0	0
1	0	0	1	1
1	0	1	0	1
1	1	0	0	0
1	1	1	1	1

 2.表达式

三.结合一二得到带3-8译码器的全减器

 1. 表达式:       

        D = Y1 + Y2 + Y4 + Y7;

        C_O = Y1 + Y4 + Y5 + Y7;

2.代码

module decoder1(
    input  wire       A,
    input  wire       B,
    input  wire       Ci,
    
    output wire       D,
    output wire       Co
);
    wire [7:0] Y;
    assign D  = Y[1] + Y[2] + Y[4] + Y[7];
    assign Co = Y[1] + Y[4] + Y[5] + Y[7];
    decoder_38 myDecoder(
        .E  (1   ), 
        .A0 (B   ), 
        .A1 (A   ), 
        .A2 (Ci  ), 
        .Y0n(Y[0]),
        .Y1n(Y[1]),
        .Y2n(Y[2]),
        .Y3n(Y[3]),
        .Y4n(Y[4]),
        .Y5n(Y[5]),
        .Y6n(Y[6]),
        .Y7n(Y[7])
    );
endmodule