一个寄存器转AXI数据流的代码

module reg2stream #(parameter WIDTH = 1024,parameter DW=8)(
	input	clk,
	input	rst,
	
	input	start,
	input	[WIDTH-1:0] regs,
	
	output	reg out_valid,
	output	reg out_last,
	output	reg [DW-1:0]	out_data,
    input   out_ready
	
	
);
	reg	start_r;
	reg	[WIDTH-1:0]	regs_r;
	reg	[$clog2(WIDTH)-1:0]	bit_cnt;
	reg	state;
	
	always @ (posedge clk or posedge rst)
	begin
		if(rst) begin
			state<=0;
		end
		else case(state)
			0:begin
				start_r<=start;
				if({start_r,start}==2'b01) begin
					regs_r<=regs;
					state<=1;
					bit_cnt<=0;
                    out_valid<=1;
                    out_last<=0;
				end
			end
			1:if(out_ready) begin
                regs_r<=regs_r>>DW;
                bit_cnt<=bit_cnt+DW;
                if(bit_cnt==WIDTH-2*DW)
                    out_last<=1;
                if(bit_cnt==WIDTH-DW) begin
                    state<=0;
                    out_valid<=0;
                end
			end
		endcase
	end
    
    always @ (*)
    out_data=regs_r[DW-1:0];
	
endmodule