所谓边沿检测,就是检测输入信号,或者FPGA内部逻辑信号的跳变,即上升沿或者下降沿的检测。
边沿检测的FPGA代码:
module top(
clk,
sig,
flag
);
input clk;input sig;
output flag;
wire rising_flag;wire falling_flag;
reg [2:0] sig_dly = 0;
always @(posedge clk)
begin
sig_dly <= {sig_dly[1:0],sig};
end
assign rising_flag = (~sig_dly[1])&sig;
assign falling_flag = sig_dly[1]&(~sig);