根据如下波形图对其进行verilog描述
解答:
‘state为下一时钟的state
对照该表不做简化得到:
module top_module (
input clk,
input a,
input b,
output q,
output state );
wire state_next;
always @(posedge clk)
state <= state_next;
assign q = ~state & ~a & b |
~state & a & ~b |
state & a & b |
state & ~a & ~b;
assign state_next = a & b | state & a | state & b;
endmodule