HDLBits答案(24)_由波形图描述电路

Build a circuit from a simulation waveform

HDLBits链接

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前言

今天更新HDLBits习题由波形图描述电路的部分，看图写代码。

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题库

Combinational circuit 1

由图可见，q=a&b

Solution：

module top_module (
    input a,
    input b,
    output q );//

    assign q = a & b; // Fix me

endmodule

Combinational circuit 2

由图列出卡诺图描述出来即可。

Solution：

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = ~a & ~b & ~c & ~d | ~a & ~b & c & d | ~a & b & ~c & d | ~a & b & c & ~d | a & ~b & ~c & d | a & ~b & c & ~d | a & b & ~c & ~d | a & b & c & d; // Fix me

endmodule

Combinational circuit 3

由波形图列出卡诺图化简可得。

Solution:

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = b & d | b & c | a & d | a & c; // Fix me

endmodule

Combinational circuit 4

与上题同理

Solution：

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = b | c; // Fix me

endmodule

Combinational circuit 5

由波形图可见这是个多路选择器，通过c路信号进行信号选择；

Solution:

module top_module (
    input [3:0] a,
    input [3:0] b,
    input [3:0] c,
    input [3:0] d,
    input [3:0] e,
    output [3:0] q );

    always @(*) begin
        case(c)
            4'd0:	q <= b;
            4'd1:	q <= e;
            4'd2:	q <= a;
            4'd3:	q <= d;
            default:q <= 4'hf;
        endcase
    end
    
endmodule

Combinational circuit 6

Solution：

module top_module (
    input [2:0] a,
    output [15:0] q ); 

    always @(*) begin
        case(a)
            3'd0:	q <= 16'h1232;
            3'd1:	q <= 16'haee0;
            3'd2:	q <= 16'h27d4;
            3'd3:	q <= 16'h5a0e;
            3'd4:	q <= 16'h2066;
            3'd5:	q <= 16'h64ce;
            3'd6:	q <= 16'hc526;
            default:q <= 16'h2f19;
        endcase
    end
    
endmodule

Sequential circuit 7

Solution：

module top_module (
    input clk,
    input a,
    output q );

    always @(posedge clk) begin
        q <= ~a;
    end
    
endmodule

Sequential circuit 8

由图可见，p为a在clock为高电平时的选通信号，q为clock下降沿触发的信号，存放p的值。

Solution:

module top_module (
    input clock,
    input a,
    output p,
    output q );

    reg clk_0;
    assign p = clock ? a : p;
    
    always @(negedge clock) begin
        q <= p;
    end
    
endmodule

Sequential circuit 9

由图可见，q应当是一个从0-6的计数器，当a为高电平时，q保持为4，直到a为低电平时，再继续计数；

Solution：

module top_module (
    input clk,
    input a,
    output [3:0] q );

    always @(posedge clk) begin
        if(a) begin
            q <= 4'd4;
        end
        else if(q == 4'd6) begin
            q <= 4'd0;
        end
        else begin
            q <= q + 4'd1;
        end
    end
    
endmodule

Sequential circuit 10

q为a,b和state的组合逻辑，列出真值表即可；

Solution：

module top_module (
    input clk,
    input a,
    input b,
    output q,
    output state  );

    assign q = a ^ b ^ state;
    
    always @(posedge clk) begin
        if(a & b) begin
            state <= 1'b1;
        end
        else if(~a & ~b) begin
            state <= 1'b0;
        end
        else begin
            state <= state;
        end
    end
    
endmodule

结语

该小结就算更新结束了，胜利就在眼前，哈哈哈！本章的解法并不唯一，大家有什么其他思路欢迎在评论区讨论交流。