Exams/ece241 2014 q5b 输出采用case语句

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
   // parameter [1:0]idle=2'd0;
    parameter [1:0]A=2'd0;
    parameter [1:0]B=2'd1;
    reg [1:0]state,next_state;
    
    always@(posedge clk,posedge areset)begin
        if(areset)
            state<=A;
        else
            state<=next_state;
    end
    
    always@(*)begin
        case(state)
            A:next_state<=x?B:A;
            B:next_state<=B;

        endcase
    end
    
    always@(*)begin
        case(state)
            A:z<=x?1:0;
            B:z<=x?0:1;
            default:z<=0;
        endcase
    end
    //assign z=(state==A & x==2'b0)?0:(state==A & x==2'd1)?1:(state==B & x==2'd1)?0:(state==B & x==2'd0)?1:0;

endmodule

关键在于最后的组合电路,输出z采用了case语句去进行解释说明.相较于assign一行语句更加简单和直观