Exams/ece241 2014 q5b

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    parameter S0=0,S1=1;
    reg  state,next_state;
    
    always@(posedge clk or posedge areset) begin
        if(areset)
            state<=S0;
        else
            state<=next_state;
    end
    
    always@(*) begin
        case(state)
            S0: next_state = x?S1:S0; 
            S1: next_state = S1; 
            default:next_state = S0;
        endcase
    end
    
    always@(*) begin//同步变化
        case(state)
            S0: z=x;
            S1: z=~x;
            default: z=1'bz;
        endcase
    end


endmodule