Retention cells

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Retention cells are sequential cells that can hold their internal state when the primary power supply is shut down and has the ability to restore the state when the power is brought up. A retention cell can be implemented in many ways. One of the most common type of retention cell is the Master/ Slave-alive retention cell. It consists of a regular flip-flop and its slave latch stores data in place during the retention operation. The latch that stores the data is powered by an ‘Always ON’ power rail and is implemented with high-threshold transistors to reduce the leakage power. It has a ‘SLEEP’ signal that controls the retention operation of the cell.

Why do we need retention cells?

In certain cases, the states of control flops needs to be retained during power-gated (PG) mode because the output of the PG cells goes to ‘X’ in PG mode. Thus when the power is back, the logic will enter metastable state. In order to avoid this we can simply reset the cells but then again we have to start from initial default state.

Consider a simple FSM that is in power-gated (PG) domain but the input is coming from an always-on (AON) domain. The FSM has four states and one input, as shown in Figure 1. Say we are in state S2 when the device moves to power gated mode, thus the power is cut off. Now once the power is restored we will have a known input value (since it is coming from AON domain), but the FSM state will be unknown, thus we have to reset the FSM and again start from state S0.

So every time out logic enters into PG mode, we have to reset that logic once power is back. Thus to fast-track the power-up recovery of states, retention cell is used as it can store the state in PG mode.
Figure 1: State transition diagram of a simple FSM

A regular positive edge triggered D – Flip flop

Before discussing about the retention cell, let us first look into a regular D – Flip flop. It has two Latches that is enabled when the enable signal to it, is high.
Figure 2: A regular positive edge-triggered D-Flip flop and a timing diagram showing how the output changes due to change in input

All the internal signals in details –

Figure 3: A timing diagram showing all the internal signals for the transition shown in Figure 2

Retention cell (Master/ Slave alive retention flop)

Figure 4: Master/Slave alive retention flop

As shown in Figure 4, the slave latch is connected to a different power rail which is always on (AON). Now when the cell moves to power gated mode, SLEEP signal is asserted and VDD power is cut-off, so the master latch is dead but the slave latch will continue storing the Data. To prevent corruption of stored data, the SLEEP signal ensure enable pin of the slave latch is low. For simplicity purpose, the reset and set of the Latches are not shown above, but the SLEEP signal also ensure set and reset remains inactive during retention mode.

Figure 5: Timing diagram showing how retention flop retains its stored value in slave latch during power gating

Issues –

• As mentioned earlier, in master/slave retention cell, the latch that stores the data in PG mode is implemented with high Vth transistor to reduce leakage power. Since low Vth transistor latch are faster, the CLK to Q delay of the cell increases as a results affects the performance.

• This master/slave alive retention cell can retrieve the state only when CLK is low because-

Figure 6: Timing diagram showing the the issue in master/slave alive retention flop (Output becomes unknown when power is back in the given scenario)

• The disadvantages of master/slave alive retention cells can be tackled by using other types of retention cells, which has its own disadvantages like increased area.

• All types of state retention cells require two types of power supplies- a switchable power supply that goes off in PG mode and an AON power supply. This introduces some complications and penalties in power routing area requirements.