module design_race;
logic clk;
logic rstn;
logic [3:0] a;
logic [3:0] b;
int clk_cnt;
initial begin
clk <= 0;
forever begin
#5ns clk <= !clk;
end
end
initial begin
#10ns;
rstn <= 1;
#10ns;
rstn <= 0;
#10ns;
rstn <= 1;
#30ns $finish(); //后加的,之前版本没有,未加之前就是无限循环
end
always @(posedge clk or negedge rstn) begin
if(rstn == 0) begin
a <= 0;
b <= 0;
end
else begin
a <= a + 1;
b <= a;
$display("@%0t a=%0d, b=%0d", $time, a, b);
end
end
endmodule
编译的结果
@5 a=x, b=x
@15 a=x, b=x
@35 a=0, b=0
@45 a=1, b=0
@55 a=2, b=1
$finish called from file "design_race.sv", line 24.
$finish at simulation time