Cs450/counter 2bc

module top_module(
    input clk,
    input areset,
    input train_valid,
    input train_taken,
    output [1:0] state
);
    reg [1:0] next_state;
    
    always@(posedge clk or posedge areset) begin
        if(areset)
            state<=2'b01;
        else
            state<=next_state;
    end
    
    always@(*) begin
        case(state)
            2'b00: next_state = (train_valid&train_taken)?2'b01:2'b00;
            2'b01: next_state = train_valid?(train_taken?2'b10:2'b00):2'b01;
            2'b10: next_state = train_valid?(train_taken?2'b11:2'b01):2'b10;
            2'b11: next_state = (train_valid&(~train_taken))?2'b10:2'b11;
        endcase
    end
     
endmodule