【HDLBits 刷题 14】Verification Reading Simulations

module top_module (
    input          sel,
    input  [7:0]   a,
    input  [7:0]   b,
    output [7:0]   out  
);

    assign out = sel?a:b ;

endmodule

Bugs nand3

module top_module (
	input      a, 
	input      b, 
	input      c, 
	output     out
);

reg    out_reg;

assign out = ~out_reg;
    
andgate inst1 (out_reg, a, b, c, 'd1, 'd1);

endmodule

Bugs mux4

module top_module (
    input  [1:0]    sel,
    input  [7:0]    a,
    input  [7:0]    b,
    input  [7:0]    c,
    input  [7:0]    d,
    output [7:0]    out 
);

    wire [7:0]  mux0, mux1;
    mux2 mux0_inst ( sel[0],    a,    b, mux0 );
    mux2 mux1_inst ( sel[0],    c,    d, mux1 );
    mux2 mux2_inst ( sel[1], mux0, mux1,  out );

endmodule

Bugs addsubz

module top_module ( 
    input              do_sub,
    input      [7:0]   a,
    input      [7:0]   b,
    output reg [7:0]   out,
    output reg         result_is_zero
);

    always @(*) begin
        case (do_sub)
          0: out = a+b;
          1: out = a-b;
        endcase

        if (out=='d0)
            result_is_zero = 'd1;
        else
        	result_is_zero = 'd0;
    end

endmodule

Bugs case

module top_module (
    input      [7:0]   code,
    output reg [3:0]   out,
    output reg         valid 
);

    always @(*) begin
     	valid = 'd1;
        case (code)
            8'h45: out = 0