Circuits--Sequence--FSM--PS/2

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已于 2024-05-15 14:55:49 修改

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分类专栏： HDLBits 文章标签： fpga开发笔记

于 2024-05-07 14:51:13 首次发布

本文链接：https://blog.csdn.net/pmlcreating/article/details/138532110

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1. PS/2 packet

module top_module(
    input clk,
    input[7:0] in,
    input reset,
    output done 
);

    parameter b_1st = 2'd0;
    parameter b_2nd = 2'd1;
    parameter b_3rd = 2'd2;
    parameter w  = 2'd3;

    reg[1:0] state;
    reg[1:0] next_state;

    always @(*) begin
        case(state)
            b_1st:  next_state = b_2nd;
            b_2nd:  next_state = b_3rd;
            b_3rd:  
                begin
                    if(in[3] == 1'b1)
                        next_state = b_1st;
                    else    next_state = w;
                end
            w:
                begin
                    if(in[3] == 1'b1)
                        next_state = b_1st;
                    else
                        next_state = w; 
                end
        endcase
    end

    always @(posedge clk) begin
        if(reset)
            state <= w;
        else
            state <= next_state;
    end

    assign done = (state == b_3rd);

endmodule

2. PS/2 datapath

module top_module(
    input clk,
    input[7:0] in,
    input reset,
    output[23:0] out_bytes,
    output done
);
 
    parameter b_1st = 2'd0;
    parameter b_2nd = 2'd1;
    parameter b_3rd = 2'd2;
    parameter d = 2'd3;
 
    reg[1:0] state;
    reg[1:0] next_state;
    reg[23:0] out_bytes_reg;
 
    always @(posedge clk) begin
        if(reset)
            state <= b_1st;
        else
            state <= next_state;
    end
 
    always @(*) begin
        case (state)
            b_1st:
                begin
                    if(in[3])
                        next_state = b_2nd;
                    else
                        next_state = b_1st;
                end
 
            b_2nd:
                begin
                    next_state = b_3rd;
                end
 
            b_3rd:
                begin
                    next_state = d;
                end
 
            d:
                begin
                    if(in[3])
                        next_state = b_2nd;
                    else
                        next_state = b_1st;
                end 
             
        endcase
    end
 
    always @(posedge clk) begin
        if(next_state == b_2nd)
            out_bytes_reg[23:16] <= in;
        else if(next_state == b_3rd)
            out_bytes_reg[15:8] <= in;
        else if(next_state == d)
            out_bytes_reg[7:0] <= in;
        else
            out_bytes_reg <= 24'd0;
    end
    assign done =(state == d);
    assign out_bytes = out_bytes_reg;
endmodule