Circuits--Sequence--FSM-- Sequence

1. Sequence recognition

module top_module(
    input clk,
    input reset,
    input in,
    output disc,
    output flag,
    output err
);

    parameter s0 = 4'd0;
    parameter s1 = 4'd1;
    parameter s2 = 4'd2;
    parameter s3 = 4'd3;
    parameter s4 = 4'd4;
    parameter s5 = 4'd5;
    parameter s6 = 4'd6;
    parameter DISC = 4'd7;
    parameter FLAG = 4'd8;
    parameter ERR = 4'd9;

    reg[3:0] state;
    reg[3:0] next_state;

    always @(*) begin
        case(state)
            s0:
                begin
                    if(in) next_state = s1;
                    else   next_state = s0;
                end
            s1:
                begin
                    if(in) next_state = s2;
                    else   next_state = s0; 
                end
            s2:
                begin
                    if(in) next_state = s3;
                    else   next_state = s0; 
                end
            s3:
                begin
                    if(in) next_state = s4;
                    else   next_state = s0;
                end
            s4:
                begin
                    if(in) next_state = s5;
                    else   next_state = s0;
                end
            s5:
                begin
                    if(in) next_state = s6;
                    else   next_state = DISC;
                end
            s6:
                begin
                    if(in) next_state = ERR;
                    else   next_state = FLAG; 
                end
            DISC:
                begin
                    if(in) next_state = s1;
                    else   next_state = s0;
                end
            FLAG:
                begin
                    if(in) next_state = s1;
                    else   next_state = s0;
                end
            ERR:
                begin
                    if(in) next_state = ERR;
                    else   next_state = s0;
                end
        endcase
    end

    always @(posedge clk) begin
        if(reset)
            state <= s0;
        else
            state <= next_state;
    end

    assign disc = (state == DISC);
    assign flag = (state == FLAG);
    assign err = (state == ERR);

endmodule