1、这个题还是挺简单的,跟刚刚一样。
module top_module(
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(*) begin
// State transition logic
if(state==ON)
next_state=(k==1)?OFF:ON;
else
next_state=(j==1)?ON:OFF;
end
always @(posedge clk, posedge areset) begin
if(areset)
state<=OFF;
else
state<=next_state;
// State flip-flops with asynchronous reset
end
// Output logic
assign out = (state == ON)?1:0;
endmodule