FPGA学习verilog实现P = (A+B)(C+D)(E+F)

最新推荐文章于 2024-08-15 19:31:42 发布

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最新推荐文章于 2024-08-15 19:31:42 发布

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本文链接：https://blog.csdn.net/qq_51152795/article/details/130948683

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层次化设计

设计目标：实现P = (A+B)*(C+D)*(E+F)

框图

代码

顶层代码TEST3_TOP

module TEST3_TOP (
    input wire [7:0]A,
    input wire [7:0]B,
    input wire [7:0]C,
    input wire [7:0]D,
    input wire [7:0]E,
    input wire [7:0]F,
    output wire [26:0]P
);

wire [8:0]add_result1;
wire [8:0]add_result2;
wire [8:0]add_result3;

ADD ADD_1(
    .A(A),
    .B(B),
    .add_result(add_result1)
);

ADD ADD_2(
    .A(C),
    .B(D),
    .add_result(add_result2)
);

ADD ADD_3(
    .A(E),
    .B(F),
    .add_result(add_result3)
);

MULT MULT_1(
    .M1(add_result1),
    .M2(add_result2),
    .M3(add_result3),
    .P(P)
);
    
endmodule

ADD代码

module ADD (
    input wire [7:0]A,
    input wire [7:0]B,

    output wire [8:0] add_result
);
    
assign add_result = A + B;

endmodule

MULT代码

 module MULT (
    input wire [8:0]M1,
    input wire [8:0]M2,
    input wire [8:0]M3,
    output wire [26:0] P
);
    
assign P = M1 * M2 * M3;

endmodule

tb文件

 `timescale 1ns/1ps

module TEST3_TOP_tb ();

reg [7:0]A;
reg [7:0]B;
reg [7:0]C;
reg [7:0]D;
reg [7:0]E;
reg [7:0]F;
wire [26:0]P;

initial begin
    A = 8'd1;
    B = 8'd1;
    C = 8'd1;
    D = 8'd1;
    E = 8'd1;
    F = 8'd1;
end

always #10 A = {$random} % 256;
always #10 B = {$random} % 256;
always #10 C = {$random} % 256;
always #10 D = {$random} % 256;
always #10 E = {$random} % 256;
always #10 F = {$random} % 256;

TEST3_TOP TEST3_TOP_1(
    .A(A),
    .B(B),
    .C(C),
    .D(D),
    .E(E),
    .F(F),
    .P(P)
);

endmodule