HDLBits 答案之 Countbcd

答案如下：

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);
    wire   a=1'b1;
    assign ena[1]=(q[3:0]==4'd9);
    assign ena[2]=ena[1]&(q[7:4]==4'd9);
    assign ena[3]=ena[2]&(q[11:8]==4'd9);
 
    BCD instance1(clk,reset,a,q[3:0]);
    BCD instance2(clk,reset,ena[1],q[7:4]);
    BCD instance3(clk,reset,ena[2],q[11:8]);
    BCD instance4(clk,reset,ena[3],q[15:12]);
endmodule

module BCD(   
    input clk,
    input reset,   // Synchronous active-high reset
    input ena,
    output [3:0] q);
    
    always @(posedge clk) begin
        if (reset )
            q<=0;
    else if (ena==1) begin
        if(q==4'd9)
             q<=0;
        else q<=q+1;
        end
    else
         q<=q;
    end
endmodule