Vivado [Place 30-574]

在Vivado15.2上设计一个简单的钟控D触发器，虽然用到了Clk，但是并不打算使用板子上的晶振，而是用开关手动获得上升沿或下降沿。在实现时，遇到了[Place 30-574]这个错误，错误提示如下所示：

[Place 30-574] Poor placement for routing between an IO pin and BUFG. 
If this sub optimal condition is acceptable for this design, 
you may use the CLOCK_DEDICATED_ROUTE 
constraint in the .xdc file to demote this message to a WARNING. 
However, the use of this override is highly discouraged. 
These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Clk_IBUF] >

解决问题的步骤如下：

1. 复制set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Clk_IBUF]到约束文件。
2. 将时钟端口的名称修改为自己设计中的名称。
3. 再次进行综合、实现，不会再报错。