- 用Verilog消除一个Glitch
module eligli(
input clk,
input rst_n,
input data,
output q_out
);
reg q_out;
reg q_dly;
// 使用一个触发器来消除
always @(posedge clk or negedge rst_n)
if(rst_n) begin q_dly <=
module eligli(
input clk,
input rst_n,
input data,
output q_out
);
reg q_out;
reg q_dly;
// 使用一个触发器来消除
always @(posedge clk or negedge rst_n)
if(rst_n) begin q_dly <=