【verilog学习9】HDLBits：Module(connect a wire to a port)

1.代码编写

module top_module ( input a, input b, output out );	
    mod_a instance1 (a,b,out); //By position
    mod_a instance1 (.in1(a),.in2(b),.out(out)); //By name
endmodule

2.提交结果

3.题目分析

connect a wire to a port:
两种方法（By position,By name）。
对于mod_a模块的定义如下：

module mod_a ( input in1, input in2, output out );
    // Module body
endmodule

By position
The syntax to connect wires to ports by position should be familiar, as it uses a C-like syntax. When instantiating a module, ports are connected left to right according to the module’s declaration. For example:
mod_a instance1 ( wa, wb, wc );（这实例化了一个模块mod_a并且起了一个实例名instance1 。将wa连到端口in1,wb到端口in2,out到端口out。
在 面向对象 的编程中，把用类创建对象的过程称为实例化。 是将一个抽象的概念类，具体到该类实物的过程。 实例化过程中一般由类名 对象名 = new 类名（参数1，参数2…参数n）构成。经module定义，mod_a成为一个抽象的概念类，instance1是mod_a类的一个实例。）
This instantiates a module of type mod_a and gives it an instance name of “instance1”, then connects signal wa (outside the new module) to the first port (in1) of the new module, wb to the second port (in2), and wc to the third port (out). One drawback of this syntax is that if the module’s port list changes, all instantiations of the module will also need to be found and changed to match the new module.
注意，这种方法需要将线的名称与端口名称顺序严格对应，在需要做出改变时相对麻烦。如果模块的端口列表发生更改，则还需要找到并更改模块的所有实例化以匹配新模块。
By name
Connecting signals to a module’s ports by name allows wires to remain correctly connected even if the port list changes. This syntax is more verbose, however.
mod_a instance2 ( .out(wc), .in1(wa), .in2(wb) );
The above line instantiates a module of type mod_a named “instance2”, then connects signal wa (outside the module) to the port named in1, wb to the port named in2, and wc to the port named out. Notice how the ordering of ports is irrelevant here because the connection will be made to the correct name, regardless of its position in the sub-module’s port list. Also notice the period immediately preceding the port name in this syntax.*