HDLBits Fsm1s

1、只是比上一个换成了同步复位。以及改用一段式来写状态机。

2、目前来看一段式采用阻塞赋值。还是三段式好看一些。逻辑更清楚。 

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    // Fill in state name declarations
    parameter A=0,B=1;
    reg present_state, next_state;
    
    
    always @(posedge clk) begin//一段式。目前还是觉得三段式好看一点。
        if (reset) begin  
            present_state=B;
            // Fill in reset logic
        end 
        else begin
            case (present_state)
                A:next_state=(in)?present_state:B;
                B:next_state=(in)?present_state:A;
                // Fill in state transition logic
            endcase 
            // State flip-flops
            present_state = next_state;   
        end
            case (present_state)
                A:out=0;
                B:out=1;
                // Fill in output logic
            endcase
        //end
    end
    //assign out=(present_state)?1:0;

endmodule