内部项目工程!!!
- 从index_store读取到的数据少一个字节(如读4B 0x01020304 却只读到 0x01020300)
解决:vivado bram ip 读端口 Permitives Output Register 勾选(读取延迟一周期) - 从concater到发送位宽转化后缺少last信号 / 发送数据包接收不到
解决:vivado axis fifo有ready信号,且axis dwidth converter内部无fifo,读入连续信号必有握手 - 在tri mode ethernet IP 实现时报错:Unroutable Placement! RAMBs driven by regional clock buffers (BUFRs and BUFHs) need to be in the same clock region as the buffers. There are not enough free RAMB sites available in the clock region where some of the buffers are placed. Some of them are listed below.
解决:在数据输出时钟添加一个BUFG